I am working with RF SoC zcu 111 gen 01 board.
My ultimate goal is first read using AXI DMA in order to pass my SYSGEN custom IP, then Custom IP is going to pass that to data converter.
I faced question to pass data to custom sysgen IP. I used AXI DMA and AXI4-stream DATA fifo 2.0. Using one axi DMA I pass data to FIFO and write out put of FIFO. It is working.
then I replace fifo using simple IP, it has slave axi interface and master axi interface. but when I tried to pass data through sysgen IP using pynq it does not happen
please could you help me to solve this.
sysgen design
