Hi, I want to send an array of data + a valid bit to an IP, specified in verilog that I have written. My IP processes this data and then returns 2 arrays of data + a output valid bit.
I want to be able to send my input data from the PS to the PL - I have considered MMIO, but it is too slow. I am considering using DMA.
How would I go about modifying my hardware so that I can interact with DMA in Vivado and then use it in PYNQ?
Hi,
Did you check this tutorial and its second part?
Hi I have, however, is there a way to send the array of data to my module without a FIFO? and read from it without one too?
I have 10 32 bit inputs that I need to transmit and then receive 20 32 bit outputs
When you talk about a FIFO, is it the block AXI4-Stream Data FIFO?
I do not know if you can enable a communication between the PS and the PL via DMA without adding DMA blocks into your block design. You could transmit something different than a stream, so that the FIFO block is not required. However the AXI DMA block seems necessary for me.