I am currently performing a test on an RFSoC 4x2 board with the default BaseOverlay where I am feeding in a 100 MHz tone (from an Agilent E8257D signal generator) into one of the ADC inputs, and am noticing some unexpectedly large distortion in the waveform:
Further analysis of the time series data seems to indicate that the signal is experiencing quasi-periodic phase jumps, although all PLL lock LEDs on the board are lit and the PLLLockStatus registers indicate lock:
print(base.radio.receiver.channel[0].adc_tile.PLLLockStatus)
2
I have also repeated these observations while using the 10 MHz output from the signal generator as a clock reference to the RFSoC 4x2 (setting register 0x147 of the LMK04828 to 0x0A), and found the same result.
For reference, I have the RFDC running at the default 4915.2 MHz sample rate, and the mixer configured as bypassed, real-to-real mode, and the decimation set to 1:
base.radio.receiver.channel[0].adc_block.MixerSettings = {'Freq': 0.0, 'PhaseOffset': 0.0, 'EventSource': 2, 'CoarseMixFreq': 16, 'MixerMode': xrfdc.MIXER_MODE_R2R, 'FineMixerScale': 1, 'MixerType': xrfdc.MIXER_TYPE_COARSE}
base.radio.receiver.channel[0].adc_block.UpdateEvent(1)
base.radio.receiver.channel[0].adc_block.DecimationFactor = 1
print(base.radio.receiver.channel[0].adc_block.BlockStatus)
{'SamplingFreq': 4.9152, 'AnalogDataPathStatus': 1, 'DigitalDataPathStatus': 17, 'DataPathClocksStatus': 1, 'IsFIFOFlagsEnabled': 3, 'IsFIFOFlagsAsserted': 3}
Is it possible that I’m configuring things incorrectly? Also, I note that in this thread, user @jacobg seems to imply that changing the mixer settings in this way is not sufficient, and one must also rebuild the .bit file after changing the appropriate mixer settings in the corresponding Vivado project. Is that really true?
