RFSoC4x2 Decimation Causes Data Loss/Sample Skipping

Support
1

Hi all,

I’m using PYNQ 2.7.0 on the RFSoC 4x2 with the base overlay.

I’m trying to change the ADC decimation factor to a factor of 40x. The only modifications of the base overlay I’ve done are changing the decimation factor in Vivado for tile 224 (leaving 226 alone), which in turn changes the required AXI4-stream clock from default of 307.2MHz to 15.36MHz. Besides that, everything is the same.

Using PYNQ, the data that comes out looks good except there is a change in phase/samples are skipped every 101 samples. My signal set up is an external RF generator set at 1497 MHz with the ADC mixer set to -1485MHz. I’m not sure what is causing this, as it doesn’t appear in the tile 226 data at the default 2x decimation factor. Since I didn’t change the samples/AXIS cycle, the packet generator should still be receiving the expected 16 bytes of data, and the clock converters should handle the new AXIS clock, so I think this issue may be on what PYNQ is expecting.

Does anyone have any ideas? Any help would be much appreciated. Thanks!

Cameron

rfdc_clocking_summary
rfdc_clocking_summary1920×1105 118 KB

signal_with_missing_data
signal_with_missing_data1920×999 120 KB

rfdc_setup
rfdc_setup1920×1105 111 KB

2

I’m not sure what the issue is, but could you try an ILA to check if the data is being received properly and if the issue is with PYNQ?

Cathal

3

I had the same issue, and it was because I hadn’t actual changed the AXI stream input clock at the rfdc or anywhere else. I was modifying the RFSoC MTS bitstream at the time, and for that I had to modify the clock generated in the clock wizard in MTSClockwizard. If you’re working on a different design you’ll have to find the corresponding clock generator that feeds into the rfdc axis clock ports, and make sure that it’s actually getting the 15.36 MHz input that it’s expecting.

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