Problem in AXI DMA Transfer in SG Mode on ZCU111

[pradeep_gautam]

Hello,
I am trying to transfer data from my IP on PL to the PYNQ running on PS. I am using the DMA in SG mode (in cyclic mode). I am attaching the code here.

I get the data , but every now and then seems to lost some data. To verify I have replaced my IP with the 32 bit counter (Tlast and Tvalid signals blocks are same what I use in case of my IP).
Here are the details of Descriptors:

1. I am using 256 descriptors, with each one requesting for 1024 samples(each sample is of size 4 bytes)
2. Descriptors are in cyclic mode (last descriptor is pointing to the first one)
3. Total no of transfer will be 0XFFFF ( with each transfer being 1024x4 bytes)
4. to verify, Each time I get the data, the difference between the first byte should of buffers should be equal to 1024.

Here are my observations;

1. I am seeing first data loss after around 6000 Desc . transfers
2. subsequently data loss happens around 6000 Desc. transfers…
3. losing some data which is every time equals to 256(no of descriptors ) x 1024 (size of transfer with each descriptor):: 263168.
4. When I use flush() for desc buffer and data buffer, the loss become more frequent.
5. Here is the output of my comparison:
   COL1: index of data mismatch
   COL2: difference of index from last data mismatch
   COL3: difference in count value
   COL1 COL2 COL3
   6071 6071 263168
   12471 6400 263168
   18882 6411 263168
   25458 6576 263168
   31805 6347 263168
   38341 6536 263168
   44622 6281 263168
   49473 4851 263168
   54786 5313 263168
   59942 5156 263168

I am not able to figure out the reason for this behavior. DMA seems to be working fine. I observed wr_count and rd_count in AXIS DATA FIFO which seems to be running fine (not having any data overflow problem in AXIS DATA FIFO connected between AXI DMA and Counter.)

I suspect the Cache behavior, but not able to either verify it or bypass the cache.
Any help on how to debug or fix the problem?

Linked-list-cyclic.ipynb (18.7 KB)