Problem in "preset.xml" of RFSoC 4x2 board files


I’m trying to design my own hardware with Vivado 2020.2 for RFSoC 4x2. Based on other posts in the forum, I downloaded the board files for RFSoC 4x2 from

I followed the tutorials in the forum to build my own hardware, but got a critical warning in Vivado when running “Block Automation” for “Zynq Ultrascale+ MPSoC” ip core.

Then I figured that this warning comes from the preset of the RFSoC 4x2 board files, which set “CONFIG.PSU__DDRC__ROW_ADDR_COUNT” to 17 in “preset.xml”.

This might be a problem in the board files provided by Could you please identify this for me? If I’m correct, where I can get reliable board files for RFSoC 4x2.


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