DDR setting for my rfsoc4x2 proccesor

Learn
1

Hello , I started to build a block diagram for my xczu48dr-ffvg1517-2-e component in vivado the proccesor called zynq ulatascale+MPSoC.
When I try to do the basic automation, It gives me and error ash shown below.
In other manuals that use zynq-700 xc7z020clg484-1 there is no such problem when I press automation.I want to use it in simple GPIO manner.
What is the difference with this proccesor?
Do you have any manual regarding how to configure this kind of proccesor?

Thanks.

[PSU-3] Setting of DDR Row Address Count (Parameter PSU__DDRC__ROW_ADDR_COUNT) to 17 is not valid when the value of Device Capacity (Parameter PSU__DDRC__DEVICE_CAPACITY) is set to 8192. The valid value for Row Address Count (Parameter PSU__DDRC__ROW_ADDR_COUNT) is 16.

image
image1792×658 84.7 KB

image
image1674×592 86.1 KB

2

Hi @yefj,

The run block design automation will only work when you select a board not a device when creating the project.

Mario

3

Hello Mario, I have made a video of step by step what I am doing shown in the link below.
I have chosen a board not only a component.
Why its not allowing to do automation?where did I go wrong?
Thanks.
2025-07-16 15-43-50.mkv

4

I see, what you are seeing is not an error. It is a warning, it is OK for you to continue.

5

Hello Mario, thank you for the responce.The problem as you can see that ever if its a wanring I dont get ddr pin on the out as shown below.the automation doesnt add no pins unlike the zynq7 proccesor.
Why is that?
Thanks.

image
image654×294 16.1 KB

6

Hi @yefj,

You may be better off asking this question on the Xilinx forums.

Mario