I have the default v2.6 pynq image loaded on the SD card on the pynq-z2 board. The boot partition of the image has boot.py file which has the base bitstream and base overlay.
I am programming the FPGA via the vitis platform as I have written some processor C code that accesses the FPGA IP blocks and manages the entire digital communication.
I have referred to link1 and link2, for getting idea of how to manage the FPGA bitstream from the Linux or processor end.
My question is when I use Vitis pynq_platform to program the bitstream into zynq, the serial command line of the pynq image OS stops. How do I make sure that Vitis can act as an FPGA manager, or we can change the bitstream after the uboot and OS is loaded on PS?
You use the PYNQ Overlay class to download your bitstream.
Did you develop a baremental C application in Vitis? Vitis is probably resetting the PS which will clear the PYNQ OS, and then trying to load the C application. It is possible to load a bitstream from Vitis or Vivado, but if you are using the design with PYNQ you should use the PYNQ Overlay class to download the bitstream.
If you want to load the bitstream at boot time, you can use the Overlay class and add/modify code in the boot.py. You can run other Python code from here to start your application.
If you have developed a C application, you need to call this from PYNQ/Python. You can do this from Python in several ways. If you are new to this I suggest you search (for example, search for CFFI which is one way to do this).
Thanks for the detailed explanation. I will try to use pynq overlay class to download the bitstream. Or use the FPGA manager class built inside the pynq.
I do not know about CFFI, I will check it out and see if the Vitis programs can be ported to the pynq image boot python files. Yes, I did use baremetal C in Vitis to code few PS registers.
I did not know about the use case of both these modules inside pynq. I will check them out and use it instead of the current baremetal code inside Vitis IDE.
