I would think that you can’t reprogram the ZYNQ cores as they’re actively running linux.
My goal is to learn more about how PYNQ operates as a whole. In my future projects, I want to be able to have my kria kv260 run Ubuntu, load a PL image, then allocate memory in kernel space for the PL.
I would think that you can’t reprogram the ZYNQ cores as they’re actively running linux.
There are certain registers that you can program at runtime, such as the PL clocks, AXI4 ports width, etc. I suggest you check the TRM for more information.
I was reading some of the pynq tutorial docs and found that when a bitstream is downloaded to the hardware manager → PL then the PS has corresponding IP drivers made available.
Does PYNQ use the HWH file to look up IPs being used and consequently load their corresponding IP drivers (like AXI)?
I did see some docs on fpgamanager but I got distracted with fpgautil. Also, I will take a look at the TRM.
I think you’ve answered all of my questions. Thank you for your help!
The last items of my concern involve driver config using Linux drivers directly instead of PYNQ and Python, but I think I need to ask those questions on the Vivado forum.
Pynq will actually make it so I don’t need to worry about that complicated setup until the end of my project… so I can focus on the actual hardware design.
Yes, those questions are more suited for the Xilinx forums.
Pynq will actually make it so I don’t need to worry about that complicated setup until the end of my project… so I can focus on the actual hardware design.