Pynq 2.7 HLS registers write-only?

I recently moved from 2.6 to 2.7 and am finding that all my HLS blocks register maps are now shown as write-only, even though I’ve not changed the IP blocks.

Any ideas what would cause this? e.g.

RegisterMap {
keep_1 = Register(keep=write-only),
keep_2 = Register(keep=write-only),
keep_3 = Register(keep=write-only),
keep_4 = Register(keep=write-only),
lastgrp = Register(lastgrp=write-only, RESERVED=write-only)


Can you clarify; are you using the same Overlay (hardware) with the new PYNQ image, or did you update your Overlay?


We are in a phase of heavy development right now so its possible some things in our overlay (.bit) have changed. The HLS blocks used in that overlay have not changed, many of our blocks use ap_ctrl_none though, maybe that ties into this.

In the past week when I noticed this we’d just migrated to pynq2.7 on the zcu111. We are also in the process of evaluating a switch to 2021.2 – IDR and Vivado seem better, scheduling in Vitis HLS for some of our common design patterns is much worse. I think I’ve ruled out the switch from .1 to .2 though because I’ve checked a bitstream from a design we still have in 2020.1 and I’m seeing the same thing.

We are going to test our pynq 2.6 sd card later today.

@cathalmccabe I’ve verified that it is the transition from pynq2.6 to 2.7 that causes this issue. The registers are shown as

RegisterMap {
keep_1 = Register(keep=0),
keep_2 = Register(keep=0),
keep_3 = Register(keep=0),
keep_4 = Register(keep=0),
lastgrp = Register(lastgrp=0, RESERVED=0)

in 2.6. While I’m not particularly concerned about how they are shown it IS a problem that pynq won’t let me read them in 2.7.

I will note that many registers in our design are clocked by an output of the RFDC and starting with the 2.7 image we need to manually call xrfclk.set_ref_clks() to bring online much of our design. Our process has been 1. download overlay, 2 call xrfclk.set_ref_clks(), 3 check registers and start loading things. Perhaps there is some sort of discovery with a timeout pynq is doing behind the scenes that would fail as the clocks haven’t started?

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Hi @baileyji,

I am to blame for these changes, we’ve seen some cases where the board hangs because the register map tries to read from a “write-only” register. In your case Vivado is exporting these registers with the “write-only” access type and therefore pynq 2.7 will not read them.

While we investigate a better way you can use the previous version of the file. Run this command in a Jupyter Lab terminal, and then restart any Jupyer Notebook you may have

wget -O /usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/

After this you should be able to see the register_map as before.