RFSoC4x2 Register Map Different Format


I am attempting to port a working ZCU111 design to the RFSoC4x2. I am seeing some discrepancy in the register map entries in my Jupyter Notebook across the boards which is causing all of my custom IP drivers to break on the 4x2. Both boards are running PYNQv2.7 and the hwh file entries for the registers I’m trying to access look identical. I’m not sure where the discrepancy is coming from or how to fix it. See details below.

Both designs were built with Vivado 2022.1 using HLS IP exported from Vitis HLS 2021.1 and integrated using an IP Integrator flow. For example, when I try to access the run register in my dac_table IP I see the correct thing on the ZCU111:

Register(run=0, RESERVED=0)

When I try this on the RFSoC4x2 I see:

Register(run=write-only, RESERVED=write-only)

Which breaks the driver… Both designs have identical entries for this register in the .hwh:

              <PROPERTY NAME="DESCRIPTION" VALUE="Data signal of run"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0"/>
                <FIELD NAME="run">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Bit 0 to 0 of run"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>

As a side note despite being “write only” the register is able to be read properly on the ZCU111 and I see the run bit turn to 1 as it should when the IP is running.

Both boards are running PYNQ v2.7.0 git id: 285d1457e64c076bbb39844afd54b38f075ad2c7. If anyone has advice for where I can track down the source of this issue please let me know.

Build / Reproduce Instructions:
The design is buildable for the ZCU111 and the RFSoC4x2 in Vivado 2022.1.

Build ZCU111:

git clone -b 2022.1 https://github.com/MazinLab/gen3-vivado-top.git --recurse-submodules
cd gen3-vivado-top
source <Vivado path>
make gen3_top

Build RFSoC4x2:

git clone -b rfsoc4x2 https://github.com/MazinLab/gen3-vivado-top.git --recurse-submodules
cd gen3-vivado-top
source <Vivado path>
make gen3_top

To run the design on a board you must download the python package:
In a terminal on a RFSoC4x2 or ZCU111 with internet access run

cd ~
mkdir ~/src
git clone https://github/com/mazinlab/mkidgen3.git ~/src/
cd ~/src/mkidgen3
git checkout develop 
source /etc/profile.d/pynq_venv.sh
sudo pip3 install fpbinary pyserial
sudo pip3 install -e ~/src/mkidgen3

The HLS source code for the dac_table IP is online here.

Bitstream + hwh + test notebook is attached for each board.
zcu111_test.zip (6.1 MB)
rfsoc4x2_test.zip (5.8 MB)

Hi Jenny,

Please see this post.

Preventing read access to write-only register is a choice we made. Because, some times some IP will not return a value when doing this and it will hang the board. If you are sure this register can be read, even if it is a write-only. You could modify the hwh file to reflect this, or revert to the way we did this in 2.6 as indicated in the post above.

Additionally, you can change the access mode if you are creating your own driver for this IP.

I am not sure why the difference between the two boards.


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Ah I see what happened. My colleague (@baileyji ) made this patch on the ZCU111 and I guess we both forgot hah. The two register.py files on the boards are indeed different versions which explains the difference in behavior I’m seeing. Thanks Mario!

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