I am trying to build an image for Zedboard using PYNQ. However, after the following message:
INFO: Copying Images from deploy to images
NOTE: Successfully copied built images to tftp dir: /tftpboot
[INFO] successfully built kernel-devsrc
cp -f /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/Zedboard/petalinux_project/build/tmp/deploy/rpm/*/kernel-devsrc-1.0-r0.*.rpm /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/Zedboard/petalinux_project/build/tmp/deploy/rpm/kernel-devsrc-1.0-r0.plnx_arm.rpm
cp --sparse=always /home/nairit/Xilinx/pynq_rootfs_arm_v2.5/bionic.arm.2.5.img /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/output/Zedboard-2.5.img
/home/nairit/PYNQ/PYNQ2.5.2/sdbuild/scripts/mount_image.sh /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/output/Zedboard-2.5.img /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard
loop0p1
loop0p2
QEMU_EXE=/opt/qemu/bin/qemu-arm-static PYNQ_BOARDDIR=/home/nairit/PYNQ/PYNQ2.5.2/boards/MyBoards/Zedboard PYNQ_BOARD=Zedboard ARCH=arm PACKAGE_PATH=/home/nairit/PYNQ/PYNQ2.5.2/boards/MyBoards/Zedboard/packages /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/scripts/install_packages.sh /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard pynq boot_leds ethernet
+ target=/home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard
+ shift
+ fss='proc run dev'
+ for fs in $fss
+ sudo mount -o bind /proc /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/proc
+ for fs in $fss
+ sudo mount -o bind /run /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/run
+ for fs in $fss
+ sudo mount -o bind /dev /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/dev
+ mkdir -p /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/ccache
+ sudo mount -o bind /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/ccache /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/ccache
+ trap unmount_special EXIT
+ export CFLAGS=
+ CFLAGS=
+ export CPPFLAGS=
+ CPPFLAGS=
+ export PATH=/usr/lib/ccache:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/petalinux/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/common/petalinux/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/gnu/microblaze/lin/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/gnu/aarch64/lin/aarch64-none/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/DocNav:/home/nairit/opt/Xilinx/SDK/2019.1/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/nairit/opt/Xilinx/Vivado/2019.1/bin:/home/nairit/opt/Xilinx/DocNav:/home/nairit/opt/Xilinx/SDK/2019.1/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/nairit/opt/Xilinx/Vivado/2019.1/bin:/opt/qemu/bin:/opt/crosstool-ng/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin
+ PATH=/usr/lib/ccache:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/petalinux/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/common/petalinux/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/gnu/microblaze/lin/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/gnu/aarch64/lin/aarch64-none/bin:/home/nairit/opt/Xilinx/PetaLinux/2019.1/tools/xsct/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/DocNav:/home/nairit/opt/Xilinx/SDK/2019.1/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/nairit/opt/Xilinx/Vivado/2019.1/bin:/home/nairit/opt/Xilinx/DocNav:/home/nairit/opt/Xilinx/SDK/2019.1/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/microblaze/lin/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/arm/lin/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/microblaze/linux_toolchain/lin64_le/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-linux/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/aarch64/lin/aarch64-none/bin:/home/nairit/opt/Xilinx/SDK/2019.1/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/nairit/opt/Xilinx/SDK/2019.1/tps/lnx64/cmake-3.3.2/bin:/home/nairit/opt/Xilinx/Vivado/2019.1/bin:/opt/qemu/bin:/opt/crosstool-ng/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin
+ export CCACHE_DIR=/ccache
+ CCACHE_DIR=/ccache
+ export CCACHE_MAXSIZE=15G
+ CCACHE_MAXSIZE=15G
+ export CCACHE_SLOPPINESS=file_macro,time_macros
+ CCACHE_SLOPPINESS=file_macro,time_macros
+ export CC=/usr/lib/ccache/gcc
+ CC=/usr/lib/ccache/gcc
+ export CXX=/usr/lib/ccache/g++
+ CXX=/usr/lib/ccache/g++
+ for p in $@
+ '[' -n /home/nairit/PYNQ/PYNQ2.5.2/boards/MyBoards/Zedboard/packages -a -e /home/nairit/PYNQ/PYNQ2.5.2/boards/MyBoards/Zedboard/packages/pynq ']'
+ f=/home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq
+ '[' -e /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq/pre.sh ']'
+ /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq/pre.sh /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard
+ set -e
+ target=/home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard
+++ dirname /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq/pre.sh
++ cd /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq
++ pwd
+ script_dir=/home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq
+ sudo mkdir -p /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/home/xilinx/pynq_git/boards
+ sudo mkdir -p /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/home/xilinx/pynq_git/dist
+ sudo cp -rfL /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/.git /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/home/xilinx/pynq_git
+ sudo cp /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq/get_revision.sh /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/home/xilinx
+ sudo cp /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq/pl_server.sh /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/usr/local/bin
+ sudo cp /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq/pl_server.service /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/lib/systemd/system
+ sudo cp /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq/pynq_hostname.sh /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/usr/local/bin
+ sudo cp /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/packages/pynq/boardname.sh /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/bionic.Zedboard/etc/profile.d
+ '[' Zedboard '!=' Unknown ']'
+ cd /home/nairit/PYNQ/PYNQ2.5.2/boards/MyBoards/Zedboard/..
+ '[' -d .git ']'
+ '[' '!' -d /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/boards/Zedboard ']'
+ cp -rf /home/nairit/PYNQ/PYNQ2.5.2/boards/MyBoards/Zedboard /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/boards/Zedboard
+ '[' -n '' ']'
+ '[' -n '' ']'
+ cd /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ
+ ./build.sh
./build.sh
A script for building bitstreams etc. for ZCU104 starts:
Script for building default overlays, microblaze bsp's and binaries.
building bitstream base.bit for ZCU104
make[1]: Entering directory '/home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/boards/ZCU104/base'
vivado -mode batch -source build_base_ip.tcl -notrace
****** Vivado v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source build_base_ip.tcl -notrace
Building color_convert_2 IP
Checking color_convert_2
Building pixel_pack_2 IP
Checking pixel_pack_2
Building pixel_unpack_2 IP
Checking pixel_unpack_2
HLS IP builds complete
INFO: [Common 17-206] Exiting Vivado at Fri May 8 11:56:32 2020...
vivado -mode batch -source base.tcl -notrace
****** Vivado v2019.1 (64-bit)
**** SW Build 2552052 on Fri May 24 14:47:09 MDT 2019
**** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
source base.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/boards/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/nairit/opt/Xilinx/Vivado/2019.1/data/ip'.
update_ip_catalog: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1406.258 ; gain = 0.000 ; free physical = 383 ; free virtual = 7503
INFO: [BD_TCL-3] Currently there is no design <base> in project, so creating one...
Wrote : </home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.srcs/sources_1/bd/base/base.bd>
INFO: [BD_TCL-4] Making design <base> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "base".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog:
xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:axi_register_slice:2.1 xilinx.com:ip:axi_iic:2.0 xilinx.com:ip:axi_gpio:2.0 xilinx.com:ip:xlslice:1.0 xilinx.com:ip:mdm:3.2 xilinx.com:ip:util_ds_buf:2.1 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:zynq_ultra_ps_e:3.3 xilinx.com:ip:pr_axi_shutdown_manager:1.0 xilinx.com:ip:xlconstant:1.1 xilinx.com:ip:xlconcat:2.1 xilinx.com:user:dff_en_reset_vector:1.0 xilinx.com:user:io_switch:1.1 xilinx.com:ip:microblaze:11.0 xilinx.com:ip:axi_bram_ctrl:4.1 xilinx.com:ip:axi_quad_spi:3.2 xilinx.com:ip:axi_timer:2.0 xilinx.com:ip:axi_vdma:6.3 xilinx.com:ip:lmb_v10:3.0 xilinx.com:ip:blk_mem_gen:8.4 xilinx.com:ip:lmb_bram_if_cntlr:4.0 xilinx.com:hls:color_convert_2:1.0 xilinx.com:ip:v_hdmi_rx_ss:3.1 xilinx.com:hls:pixel_pack_2:1.0 xilinx.com:ip:axis_subset_converter:1.1 xilinx.com:ip:axis_register_slice:1.1 xilinx.com:ip:v_hdmi_tx_ss:3.1 xilinx.com:hls:pixel_unpack_2:1.0 xilinx.com:ip:vid_phy_controller:2.2 .
create_bd_cell: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1592.250 ; gain = 37.301 ; free physical = 191 ; free virtual = 7334
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_0: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide.
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_0: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide.
WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/io_switch/io_data_i is being overridden by the user. This pin will not be connected as a part of interface connection io
WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/io_switch/io_data_o is being overridden by the user. This pin will not be connected as a part of interface connection io
WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/io_switch/io_tri_o is being overridden by the user. This pin will not be connected as a part of interface connection io
WARNING: [BD 41-1306] The connection to interface pin /iop_pmod0/intr/gpio_io_o is being overridden by the user. This pin will not be connected as a part of interface connection GPIO
WARNING: [BD 41-1731] Type mismatch between connected pins: /iop_pmod0/clk_100M(clk) and /iop_pmod0/dff_en_reset_vector_0/clk(undef)
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-2] base_mb_bram_ctrl_1: In IP Integrator, please note that memory depth value gets calculated based on the Data Width of the IP and Address range selected in the Address Editor.Incase a validation error occured on the range of this parameter, please check if the selected Data width and the Address Range are valid. For valid Data width and memory depth values, please refer to the AXI BRAM Controller Product Guide.
INFO: [xilinx.com:ip:axi_bram_ctrl:4.1-1] base_mb_bram_ctrl_1: In IP Integrator, The Maximum address range supported is 2G. Selecting the address range more than 2G in the address editor may resets the value of Memory depth to default value (1024). please refer to the AXI BRAM Controller Product Guide.
WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/io_switch/io_data_i is being overridden by the user. This pin will not be connected as a part of interface connection io
WARNING: [BD 41-1306] The connection to interface pin /iop_pmod1/io_switch/io_data_o is being overridden by the user. This pin will not be connected as a part of interface connection io
...
The terminal output finally freezes at:
...
bd_e030_util_vector_logic_0_0_synth_1: /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_e030_util_vector_logic_0_0_synth_1/runme.log
bd_e030_axi_crossbar_0_synth_1: /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/bd_e030_axi_crossbar_0_synth_1/runme.log
synth_1: /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/synth_1/runme.log
[Fri May 8 12:02:13 2020] Launched impl_1...
Run output will be captured here: /home/nairit/PYNQ/PYNQ2.5.2/sdbuild/build/PYNQ/boards/ZCU104/base/base/base.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:01:46 ; elapsed = 00:02:11 . Memory (MB): peak = 4372.469 ; gain = 2661.504 ; free physical = 148 ; free virtual = 6095
[Fri May 8 12:02:13 2020] Waiting for impl_1 to finish...
My OS is ZorinOS15 (based on Ubuntu 18.04) in a VirtualBox Version 6.1.6 with guest additions installed. I am using Vivado, SDK and Petalinux 2019.1 and PYNQ 2.5 cloned using:
git clone https://github.com/Xilinx/PYNQ.git
I tried with a Ubuntu 18.04.1 in a VirtualBox 6.1.6 with Vivado, SDK,Petalinux 2019.1 and PYNQ as well but with the same problem.
I tried cloning the PYNQ branches 2.5.1 and and 2.5.2 separately and running the build process again. But again the same problem.
I am using a prebuilt PYNQ rootfs arm v2.5 image file and the Petalinux BSP avnet-digilent-zedboard-v2019.1-final.bsp downloaded from Xilinx.
I created a folder Zedboard inside which I put the BSP file and a Zedboard.spec file. The contents of the Zedboard.spec file are:
ARCH_Zedboard := arm
BSP_Zedboard := avnet-digilent-zedboard-v2019.1-final.bsp
BITSTREAM_Zedboard :=
STAGE4_PACKAGES_Zedboard := pynq boot_leds ethernet
I tried running the codes:
make PREBUILT=/home/nairit/Xilinx/pynq_rootfs_arm_v2.5/bionic.arm.2.5.img BOARDS=Zedboard
and
make PREBUILT=/home/nairit/Xilinx/pynq_rootfs_arm_v2.5/bionic.arm.2.5.img BOARDDIR=/home/nairit/PYNQ/PYNQ2.5.2/boards/MyBoards
but end up with the same problem.
I searched the forum and found
PYNQ 2.5.1 custom board building mixed with pynq boards
but could not find what needs to be corrected.
How can I solve the problem?
Is there any reason for building the bitstreams for ZCU104 even if I want to build image ONLY FOR a custom board Zedboard ?
