PYNQ: PYTHON PRODUCTIVITY

Pynq complains, missing CONNECTIVITY?

Hello,

I just made a first super simple vivado design just containing a memory.
xclbin is generated using vitis
When I try to load this xclbin into pynq overlay, I get this error:

(base) emp137@ubuntustandalone-emp106:~/workspace/vitistest_201106$ ./test.py
Worker name: ubuntustandalone-emp106 | shell version: "xilinx_u50_gen3x16_xdma_201920_3"
> /home/emp137@intra.advenica.com/workspace/vitistest_201106/test.py(159)<module>()
-> ol_w0 = pynq.Overlay(xclbin, device=daskdev_w0)
(Pdb) c
Traceback (most recent call last):
  File "./test.py", line 159, in <module>
    ol_w0 = pynq.Overlay(xclbin, device=daskdev_w0)
  File "/home/emp137@intra.advenica.com/anaconda3/lib/python3.7/site-packages/pynq/overlay.py", line 330, in __init__
    self.parser = self.device.get_bitfile_metadata(self.bitfile_name)
  File "./test.py", line 112, in get_bitfile_metadata
    return pynq.pl_server.xclbin_parser.XclBin(bitfile_name)
  File "/home/emp137@intra.advenica.com/anaconda3/lib/python3.7/site-packages/pynq/pl_server/xclbin_parser.py", line 288, in __init__
    self.ip_dict, self.mem_dict = _xclbin_to_dicts(filename)
  File "/home/emp137@intra.advenica.com/anaconda3/lib/python3.7/site-packages/pynq/pl_server/xclbin_parser.py", line 244, in _xclbin_to_dicts
    sections[xclbin.AXLF_SECTION_KIND.CONNECTIVITY])

I think it is related to the fact my xclbin does not have a section called CONNECTIVITY

==============================================================================
xclbin Information
------------------
   Generated by:           v++ (2020.1) on Wed May 27 19:54:35 MDT 2020
   Version:                2.7.766
   Kernels:                test_201106_bd_1_wrapper
   Signature:              
   Content:                Bitstream
   UUID (xclbin):          3bb535f4-e547-4564-ab93-c3770c589650
   UUID (IINTF):           862c7020a250293e32036f19956669e5
   Sections:               BITSTREAM, MEM_TOPOLOGY, IP_LAYOUT, 
                           CLOCK_FREQ_TOPOLOGY, BUILD_METADATA, 
                           EMBEDDED_METADATA, SYSTEM_METADATA, PARTITION_METADATA

But I do not know the internals of the xclbin. Should I have a “CONNECTIVITY” section, and what does it contain?
Right now my vivado deign only contains a axi4-lite control interface “s_axi_control”, a clock “ap_clk” and a reset “a_rst_n”. No interrupts, no master axi ports.

Any ideas how to get this to work in pynq?
I have no problem adding ports/interrupts/etc if this is what pynq requires.

Thank you
/Peter

Hi @petertufvesson, I am looking into this. Would it be possible to generate the XCLBIN with a different XRT version, let’s say 2.6.655 and report the xclbin Information?

Mario

@petertufvesson can you apply this change to pynq/pl_server/xclbin_parser.py

This change will allow you to use xclbin without CONNECTIVITY section

Mario