PYNQ: PYTHON PRODUCTIVITY

Using vitis to create xclbin for the PYNQ-Z1 board

Hi there,
I am using vitis_hls to build a kernel for a PYNQ-Z1 board. Currently, I am manually creating a block design in Vivado, which includes the aforementioned kernel.

Is it possible to use Vitis to create the bitstream (xclbin) for this board? I mean in the same way as bitstreams are created for AWS F1 instances.

Any example you could point me too?

Best,
Medrano