PYNQ error with trace_cntrl_32

Hello everyone,

I am trying to deploy some FINN models on a ZCU102. As the board is not supported I am building PYNQ specifically for it. I cloned the PYNQ-GitHub repository and I have created a ZCU102 subfolder in the boards folder. That folder contains the bsp and s .spec file. The spec file looks as follows :

ARCH_ZCU102 := aarch64
BSP_ZCU102 := xilinx-zcu102-v2020.2-final.bsp
FPGA_MANAGER_ZCU102 := 1

I have not specified a bitstream, as I will be using the custom one present in the bsp. I am able to compile the embedded-linux up to a late step, simply by calling the make command in the sdbuild folder . I am getting this error :

/opt/qemu/bin/qemu-aarch64-static -version | fgrep 5.2.0
qemu-aarch64 version 5.2.0
vivado -version | fgrep 2020.2
Vivado v2020.2 (64-bit)
vitis -version | fgrep 2020.2
****** Vitis v2020.2 (64-bit)
which petalinux-config
/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/common/petalinux/bin/petalinux-config
which arm-linux-gnueabihf-gcc
/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin/arm-linux-gnueabihf-gcc
which microblaze-xilinx-elf-gcc
/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/microblaze/lin/bin/microblaze-xilinx-elf-gcc
which ct-ng
/opt/crosstool-ng/bin/ct-ng
bash /home/<user>/PYNQ/sdbuild/scripts/check_env.sh
Checking system for required packages:
bc gperf bison flex texi2html texinfo help2man gawk libtool libtool-bin build-essential automake libglib2.0-dev device-tree-compiler qemu-user-static binfmt-support multistrap git lib32z1 libbz2-1.0 lib32stdc++6 libssl-dev kpartx zerofree u-boot-tools rpm2cpio libsdl1.2-dev rsync python3-pip gcc-multilib libidn11 curl libncurses5-dev lib32ncurses5
sudo rm -rf /home/<user>/PYNQ/sdbuild/build/focal.aarch64
mkdir /home/<user>/PYNQ/sdbuild/build/focal.aarch64
(cd /home/<user>/PYNQ/sdbuild/build/focal.aarch64 && sudo tar -xf /home/<user>/PYNQ/sdbuild/build/focal.aarch64.stage2.tar.gz)
QEMU_EXE=/opt/qemu/bin/qemu-aarch64-static PYNQ_BOARD=Unknown ARCH=aarch64 /home/<user>/PYNQ/sdbuild/scripts/install_packages.sh /home/<user>/PYNQ/sdbuild/build/focal.aarch64 pynq x11 resizefs
+ target=/home/<user>/PYNQ/sdbuild/build/focal.aarch64
+ shift
+ fss='proc run dev'
+ for fs in $fss
+ sudo mount -o bind /proc /home/<user>/PYNQ/sdbuild/build/focal.aarch64/proc
+ for fs in $fss
+ sudo mount -o bind /run /home/<user>/PYNQ/sdbuild/build/focal.aarch64/run
+ for fs in $fss
+ sudo mount -o bind /dev /home/<user>/PYNQ/sdbuild/build/focal.aarch64/dev
+ mkdir -p /home/<user>/PYNQ/sdbuild/build/focal.aarch64/ccache
+ sudo mount -o bind /home/<user>/PYNQ/sdbuild/ccache /home/<user>/PYNQ/sdbuild/build/focal.aarch64/ccache
+ trap unmount_special EXIT
+ export CFLAGS=
+ CFLAGS=
+ export CPPFLAGS=
+ CPPFLAGS=
+ export PATH=/usr/lib/ccache:/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/bin:/tools/Xilinx/vivado_vitis/Model_Composer/2020.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/aietools/bin:/tools/Xilinx/vivado_vitis/Vivado/2020.2/bin:/tools/Xilinx/DocNav:/tools/Xilinx/Vivado/2020.1/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/petalinux/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/common/petalinux/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/gnu/microblaze/lin/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/gnu/aarch64/lin/aarch64-none/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/bin:/tools/Xilinx/vivado_vitis/Model_Composer/2020.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/aietools/bin:/tools/Xilinx/vivado_vitis/Vivado/2020.2/bin:/tools/Xilinx/DocNav:/home/<user>/anaconda3/condabin:/opt/qemu/bin:/opt/crosstool-ng/bin:/opt/qemu/bin:/opt/crosstool-ng/bin:/opt/qemu/bin:/opt/crosstool-ng/bin:/home/<user>/.local/bin:/home/<user>/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin
+ PATH=/usr/lib/ccache:/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/bin:/tools/Xilinx/vivado_vitis/Model_Composer/2020.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/aietools/bin:/tools/Xilinx/vivado_vitis/Vivado/2020.2/bin:/tools/Xilinx/DocNav:/tools/Xilinx/Vivado/2020.1/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/petalinux/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/common/petalinux/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/gnu/microblaze/lin/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/gnu/armr5/lin/gcc-arm-none-eabi/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/gnu/aarch64/lin/aarch64-none/bin:/home/<user>/meteors/zcu_102_linux/petalinux_tools/tools/xsct/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/bin:/tools/Xilinx/vivado_vitis/Model_Composer/2020.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/microblaze/lin/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/arm/lin/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/microblaze/linux_toolchain/lin64_le/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch64/lin/aarch64-linux/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/aarch64/lin/aarch64-none/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/gnu/armr5/lin/gcc-arm-none-eabi/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/tps/lnx64/cmake-3.3.2/bin:/tools/Xilinx/vivado_vitis/Vitis/2020.2/aietools/bin:/tools/Xilinx/vivado_vitis/Vivado/2020.2/bin:/tools/Xilinx/DocNav:/home/<user>/anaconda3/condabin:/opt/qemu/bin:/opt/crosstool-ng/bin:/opt/qemu/bin:/opt/crosstool-ng/bin:/opt/qemu/bin:/opt/crosstool-ng/bin:/home/<user>/.local/bin:/home/<user>/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin
+ export CCACHE_DIR=/ccache
+ CCACHE_DIR=/ccache
+ export CCACHE_MAXSIZE=15G
+ CCACHE_MAXSIZE=15G
+ export CCACHE_SLOPPINESS=file_macro,time_macros
+ CCACHE_SLOPPINESS=file_macro,time_macros
+ export CC=/usr/lib/ccache/gcc
+ CC=/usr/lib/ccache/gcc
+ export CXX=/usr/lib/ccache/g++
+ CXX=/usr/lib/ccache/g++
+ hostresolvfile=/etc/resolv.conf
+ targetresolvfile=/home/<user>/PYNQ/sdbuild/build/focal.aarch64/etc/resolv.conf
+ [[ -L /home/<user>/PYNQ/sdbuild/build/focal.aarch64/etc/resolv.conf ]]
+ sudo mv /home/<user>/PYNQ/sdbuild/build/focal.aarch64/etc/resolv.conf /home/<user>/PYNQ/sdbuild/build/focal.aarch64/etc/resolv.conf.link
+ sudo cp -L /etc/resolv.conf /home/<user>/PYNQ/sdbuild/build/focal.aarch64/etc/resolv.conf
+ for p in $@
+ '[' -n '' -a -e /pynq ']'
+ f=/home/<user>/PYNQ/sdbuild/packages/pynq
+ '[' -e /home/<user>/PYNQ/sdbuild/packages/pynq/pre.sh ']'
+ /home/<user>/PYNQ/sdbuild/packages/pynq/pre.sh /home/<user>/PYNQ/sdbuild/build/focal.aarch64
+ set -e
+ target=/home/<user>/PYNQ/sdbuild/build/focal.aarch64
+++ dirname /home/<user>/PYNQ/sdbuild/packages/pynq/pre.sh
++ cd /home/<user>/PYNQ/sdbuild/packages/pynq
++ pwd
+ script_dir=/home/<user>/PYNQ/sdbuild/packages/pynq
+ sudo mkdir -p /home/<user>/PYNQ/sdbuild/build/focal.aarch64/home/xilinx/pynq_git/boards
+ sudo mkdir -p /home/<user>/PYNQ/sdbuild/build/focal.aarch64/home/xilinx/pynq_git/dist
+ sudo cp /home/<user>/PYNQ/sdbuild/packages/pynq/pl_server.sh /home/<user>/PYNQ/sdbuild/build/focal.aarch64/usr/local/bin
+ sudo cp /home/<user>/PYNQ/sdbuild/packages/pynq/pl_server.service /home/<user>/PYNQ/sdbuild/build/focal.aarch64/lib/systemd/system
+ sudo cp /home/<user>/PYNQ/sdbuild/packages/pynq/pynq_hostname.sh /home/<user>/PYNQ/sdbuild/build/focal.aarch64/usr/local/bin
+ sudo cp /home/<user>/PYNQ/sdbuild/packages/pynq/boardname.sh /home/<user>/PYNQ/sdbuild/build/focal.aarch64/etc/profile.d
++ date +%Y_%m_%d
++ git rev-parse --short=7 --verify HEAD
+ echo 'Release 2022_03_29 59515a9'
+ '[' Unknown '!=' Unknown ']'
+ sudo cp -rf /home/<user>/PYNQ/sdbuild/build/PYNQ/REVISION /home/<user>/PYNQ/sdbuild/build/focal.aarch64/home/xilinx/REVISION
+ sudo cp -rf /home/<user>/PYNQ/sdbuild/build/PYNQ/REVISION /home/<user>/PYNQ/sdbuild/build/focal.aarch64/boot/REVISION
+ '[' -d /usr/local/share/fatfs_contents ']'
+ '[' -n '' ']'
+ '[' -n '' ']'
+ cd /home/<user>/PYNQ/sdbuild/build/PYNQ
+ ./build.sh
./build.sh

Script for building default overlays, microblaze bsp's and binaries.

building bitstream logictools.bit for Pynq-Z2
make[1]: Entering directory '/home/<user>/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z2/logictools'
rm -rf logictools *.jou *.log NA .Xil
make[1]: Leaving directory '/home/<user>/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z2/logictools'
make[1]: Entering directory '/home/<user>/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z2/logictools'
vivado -mode batch -source build_ip.tcl -notrace

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source build_ip.tcl -notrace
Building trace_cntrl_32 IP

****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source /tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user '<user>' on host '5gtower' (Linux_x86_64 version 5.4.0-105-generic) on Tue Mar 29 15:08:35 CEST 2022
INFO: [HLS 200-10] On os Ubuntu 18.04.6 LTS
INFO: [HLS 200-10] In directory '/home/<user>/PYNQ/sdbuild/build/PYNQ/boards/ip/hls'
Sourcing Tcl script 'trace_cntrl_32/script.tcl'
INFO: [HLS 200-1510] Running: open_project trace_cntrl_32 
INFO: [HLS 200-10] Opening project '/home/<user>/PYNQ/sdbuild/build/PYNQ/boards/ip/hls/trace_cntrl_32'.
INFO: [HLS 200-1510] Running: set_top trace_cntrl_32 
INFO: [HLS 200-1510] Running: add_files trace_cntrl_32/trace_cntrl_32.cpp 
INFO: [HLS 200-10] Adding design file 'trace_cntrl_32/trace_cntrl_32.cpp' to the project
INFO: [HLS 200-1510] Running: open_solution solution1 
INFO: [HLS 200-10] Opening solution '/home/<user>/PYNQ/sdbuild/build/PYNQ/boards/ip/hls/trace_cntrl_32/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020-clg484-1'
INFO: [HLS 200-1505] Using flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1464] Running solution command: config_export -description {Controller for the trace analyzer with 32-bit data}
INFO: [HLS 200-1464] Running solution command: config_export -display_name {Trace Analyzer Controller with 32 Bits Data}
INFO: [HLS 200-1464] Running solution command: config_export -format=ip_catalog
INFO: [HLS 200-1464] Running solution command: config_export -version=1.4
INFO: [HLS 200-1510] Running: set_part xc7z020clg484-1 
INFO: [HLS 200-1510] Running: create_clock -period 10 
INFO: [HLS 200-1510] Running: csynth_design 
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 191.239 MB.
INFO: [HLS 200-10] Analyzing design file 'trace_cntrl_32/trace_cntrl_32.cpp' ... 
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 2.9 seconds. CPU system time: 0.34 seconds. Elapsed time: 2.76 seconds; current allocated memory: 192.338 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_user_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::read(hls::axis<ap_int<32>, 1ul, 1ul, 1ul>&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:283:50)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_dest_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::read(hls::axis<ap_int<32>, 1ul, 1ul, 1ul>&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:286:25)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_id_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::read(hls::axis<ap_int<32>, 1ul, 1ul, 1ul>&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:285:67)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_user_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::read(hls::axis<ap_int<32>, 1ul, 1ul, 1ul>&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:285:36)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_dest_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::read(hls::axis<ap_int<32>, 1ul, 1ul, 1ul>&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:284:39)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_id_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::read(hls::axis<ap_int<32>, 1ul, 1ul, 1ul>&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:284:23)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_user_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::write(hls::axis<ap_int<32>, 1ul, 1ul, 1ul> const&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:304:51)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_dest_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::write(hls::axis<ap_int<32>, 1ul, 1ul, 1ul> const&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:307:26)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_id_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::write(hls::axis<ap_int<32>, 1ul, 1ul, 1ul> const&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:306:68)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_user_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::write(hls::axis<ap_int<32>, 1ul, 1ul, 1ul> const&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:306:37)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_dest_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::write(hls::axis<ap_int<32>, 1ul, 1ul, 1ul> const&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:305:40)
INFO: [HLS 214-131] Inlining function 'hls::axis<ap_int<32>, 1ul, 1ul, 1ul>::get_id_ptr()' into 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::write(hls::axis<ap_int<32>, 1ul, 1ul, 1ul> const&)' (/tools/Xilinx/vivado_vitis/Vitis_HLS/2020.2/common/technology/autopilot/ap_axi_sdata.h:305:24)
INFO: [HLS 214-131] Inlining function 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::read(hls::axis<ap_int<32>, 1ul, 1ul, 1ul>&)' into 'trace_cntrl_32(hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>&, hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>&, ap_int<32>, int)' (trace_cntrl_32/trace_cntrl_32.cpp:30:11)
INFO: [HLS 214-131] Inlining function 'hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>::write(hls::axis<ap_int<32>, 1ul, 1ul, 1ul> const&)' into 'trace_cntrl_32(hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>&, hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>&, ap_int<32>, int)' (trace_cntrl_32/trace_cntrl_32.cpp:36:16)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 2.81 seconds. CPU system time: 0.29 seconds. Elapsed time: 3.11 seconds; current allocated memory: 193.525 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 193.526 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 200.249 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 208.720 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.15 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 238.899 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 235.616 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'trace_cntrl_32' ...
WARNING: [SYN 201-107] Renaming port name 'trace_cntrl_32/length' to 'trace_cntrl_32/length_r' to avoid the conflict with HDL keywords or other object names.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'trace_cntrl_32' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_28_1'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 3, loop 'VITIS_LOOP_28_1'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.03 seconds; current allocated memory: 235.887 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 236.177 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'trace_cntrl_32' 
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/trace_32_V_data_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/trace_32_V_keep_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/trace_32_V_strb_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/trace_32_V_user_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/trace_32_V_last_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/trace_32_V_id_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/trace_32_V_dest_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/capture_32_V_data_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/capture_32_V_keep_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/capture_32_V_strb_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/capture_32_V_user_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/capture_32_V_last_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/capture_32_V_id_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/capture_32_V_dest_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/trigger' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'trace_cntrl_32/length_r' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'trace_cntrl_32' to 's_axilite & ap_ctrl_hs'.
INFO: [RTGEN 206-100] Bundling port 'trigger', 'length_r' and 'return' to AXI-Lite port trace_cntrl.
INFO: [RTGEN 206-100] Finished creating RTL model for 'trace_cntrl_32'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.04 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 236.992 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.63 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.64 seconds; current allocated memory: 245.177 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for trace_cntrl_32.
INFO: [VLOG 209-307] Generating Verilog RTL for trace_cntrl_32.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 149.43 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 6.83 seconds. CPU system time: 0.66 seconds. Elapsed time: 7.02 seconds; current allocated memory: 245.511 MB.
INFO: [HLS 200-1510] Running: export_design -format ip_catalog -description Controller for the trace analyzer with 32-bit data -version 1.4 -display_name Trace Analyzer Controller with 32 Bits Data 
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
bad lexical cast: source type value could not be interpreted as target
    while executing
"rdi::set_property core_revision 2203291508 {component component_1}"
    invoked from within
"set_property core_revision $Revision $core"
    (file "run_ippack.tcl" line 974)
INFO: [Common 17-206] Exiting Vivado at Tue Mar 29 15:08:52 2022...
ERROR: [IMPL 213-28] Failed to generate IP.
INFO: [HLS 200-111] Finished Command export_design CPU user time: 9.34 seconds. CPU system time: 0.78 seconds. Elapsed time: 11.32 seconds; current allocated memory: 249.099 MB.
command 'ap_source' returned error code
    while executing
"source trace_cntrl_32/script.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

INFO: [HLS 200-112] Total CPU user time: 18.07 seconds. Total CPU system time: 1.88 seconds. Total elapsed time: 19.79 seconds; peak allocated memory: 245.177 MB.
INFO: [Common 17-206] Exiting vitis_hls at Tue Mar 29 15:08:55 2022...
child process exited abnormally
INFO: [Common 17-206] Exiting Vivado at Tue Mar 29 15:08:55 2022...
makefile:10: recipe for target 'hls_ip' failed
make[1]: *** [hls_ip] Error 1
make[1]: Leaving directory '/home/<user>/PYNQ/sdbuild/build/PYNQ/boards/Pynq-Z2/logictools'
+ unmount_special
+ for fs in $fss
+ sudo umount -l /home/<user>/PYNQ/sdbuild/build/focal.aarch64/proc
+ for fs in $fss
+ sudo umount -l /home/<user>/PYNQ/sdbuild/build/focal.aarch64/run
+ for fs in $fss
+ sudo umount -l /home/<user>/PYNQ/sdbuild/build/focal.aarch64/dev
+ sudo umount -l /home/<user>/PYNQ/sdbuild/build/focal.aarch64/ccache
+ rmdir /home/<user>/PYNQ/sdbuild/build/focal.aarch64/ccache
Makefile:344: recipe for target '/home/<user>/PYNQ/sdbuild/output/focal.aarch64.2.7.0.tar.gz' failed
make: *** [/home/<user>/PYNQ/sdbuild/output/focal.aarch64.2.7.0.tar.gz] Error 2

My understanding is that something goes wrong with the generatio of the trace_cntrl_32 unit for the Pynq-Z2 board. Precisely that happens in run_ippack.tcl at line 974, which is as follows :

set_property core_revision $Revision $core

Any help on why this error might occur would be much appreciated. Sorry for the beginner question.

1 Like

Hi @laserbeam,

Did you patch the Y2K22 bug? https://support.xilinx.com/s/article/76960?language=en_US

I helped someone else before to get PYNQ running on the official Ubuntu image for ZCU102, you can check it here An Attempt to Install PYNQ on Ubuntu for ZCU102, this can be more effective for you instead of building the PYNQ image.

Mario

1 Like

Hello @marioruiz,

you are right. I had forgotten to patch the 2020.2 version on my machine. Thanks for the link, I will keep you posted on how much progress I make with it.

BR,

Vittorio

Hello everyone,

so the build process now goes on until I encounter this error :

Attempting to get a license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xczu7ev'
INFO: [Common 17-83] Releasing license: Implementation
41 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors encountered.
write_bitstream failed
ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
base_i/video/hdmi_out/frontend/inst/v_hdmi_tx/inst (<encrypted cellview>)
base_i/video/hdmi_in/frontend/inst/v_hdmi_rx/inst (<encrypted cellview>)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

I guess this is pretty self-explainatory : I do not have the HDMI-IP on my machine. Is there a way to circumvent this (e.g. disable HDMI outputs), except requesting a trial license (as specified here ) ?

Hi there,

Are you using the prebuilt pynq sdist? You can download it from the release on the pynq github repo here’s the link. This should prevent you from rebuilding overlays for Z1 and ZCU104, and circumvent the licensing issue. Also, if you aren’t already I highly recommend also adding the prebuilt board agnostic image, so you don’t have to rebuild the entire linux filesystem from here.

If you add these to your make command

make BOARDDIR=<your_boarddir> PYNQ_SDIST=<sdist_tarball_path> PREBUILT=<agnostic_image_path>

Build will hopefully progress!

Thanks
Shawn

Hello Everyone,

sorry for the loner delay in replying. I was able to generate a PYNQ image from scratch by requesting a trial-license for the HDMI-IPs.

The board boots fine and we can connect to it. We are testing weather we can deploy our FINN models to it. I am confused a little by the FPGA status LED which remains red.

I will keep you up to speed with the process :wink:

1 Like

Hello everyone,

As promised, I would keep you posted. When running the cybersecurity example I get a “No Devices Found” error. More is posted below :

xilinx@pynq:~/finn-cybsec-mlp-demo/driver$ python3 validate-unsw-nb15.py --batchsize 1000
Loading dataset...
Initializing driver, flashing bitfile...
/usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/pl_server/device.py:79: UserWarning: No devices found, is the XRT environment sourced?
  warnings.warn(
Traceback (most recent call last):
  File "validate-unsw-nb15.py", line 80, in <module>
    driver = FINNExampleOverlay(
  File "/home/xilinx/finn-cybsec-mlp-demo/driver/driver_base.py", line 80, in __init__
    super().__init__(bitfile_name, download=download, device=device)
  File "/usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/overlay.py", line 336, in __init__
    super().__init__(bitfile_name, dtbo, partial=False, device=device)
  File "/usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/bitstream.py", line 111, in __init__
    device = Device.active_device
  File "/usr/local/share/pynq-venv/lib/python3.8/site-packages/pynq/pl_server/device.py", line 94, in active_device
    raise RuntimeError("No Devices Found")
RuntimeError: No Devices Found

Maybe some of you has a suggestion ?

Hi,

Did you source the venv as discussed here Accessing an overlay from multiple python interpreters - #6 by baileyji?

Mario

Hello @marioruiz,

I have followed the steps specified by baileyji, I am getting the same error :

In [4]: pynq.Overlay("/home/xilinx/finn-cybsec-mlp-demo/bitfile")
/home/xilinx/pynq/pl_server/device.py:79: UserWarning: No devices found, is the XRT environment sourced?
  warnings.warn(
---------------------------------------------------------------------------
RuntimeError                              Traceback (most recent call last)
<ipython-input-4-a5971b23cb9f> in <module>
----> 1 pynq.Overlay("/home/xilinx/finn-cybsec-mlp-demo/bitfile")

/home/xilinx/pynq/overlay.py in __init__(self, bitfile_name, dtbo, download, ignore_version, device)
    334 
    335         """
--> 336         super().__init__(bitfile_name, dtbo, partial=False, device=device)
    337 
    338         self._register_drivers()

/home/xilinx/pynq/bitstream.py in __init__(self, bitfile_name, dtbo, partial, device)
    109         if device is None:
    110             from .pl_server.device import Device
--> 111             device = Device.active_device
    112         self.device = device
    113 

/home/xilinx/pynq/pl_server/device.py in active_device(cls)
     92         if not hasattr(cls, '_active_device'):
     93             if len(cls.devices) == 0:
---> 94                 raise RuntimeError("No Devices Found")
     95             cls._active_device = cls.devices[0]
     96         return cls._active_device

RuntimeError: No Devices Found

Hi,

Are you able to run xbutil dump in the command line?

I also noticed that you are running as regular user, to interact with the FPGA, sudo is needed.

Mario

Hello @marioruiz,

No I am not able to do so, as the command is not found. Maybe I have done something wrong in the build process ?

Hi,

Perhaps, xbutil is not included in the path. Can you check if it is present in /usr/bin/xbutil

Do you have xrt in the STAGE4_PACKAGES variable within the .spec file? Something like this PYNQ/ZCU104.spec at master · Xilinx/PYNQ · GitHub

Mario

Hello @marioruiz,

I have rebuilt everything. I had a typo in the Makefile which prevented the building of the xrt library.

Executing the steps reported by @baileyji return a "No module named ‘pynq’ " error. It is reported below : xilinx@pynq:~/finn-cybsec-mlp-demo/driver$ su Password: root@pynq:/home/xilinx/finn-cybsec-mlp-demo/driver# . /etc/environment root@pynq:/home/xilinx/finn-cybsec-mlp-demo/driver# for f in /etc/profile.d/*.sh; do source $f; done (pynq-venv) root@pynq:/home/xilinx/finn-cybsec-mlp-demo/driver# python3.8 validate-unsw-nb15.py --batchsize 1000 Traceback (most recent call last): File "validate-unsw-nb15.py", line 31, in <module> from driver import io_shape_dict File "/home/xilinx/finn-cybsec-mlp-demo/driver/driver.py", line 34, in <module> from driver_base import FINNExampleOverlay File "/home/xilinx/finn-cybsec-mlp-demo/driver/driver_base.py", line 32, in <module> import pynq ModuleNotFoundError: No module named 'pynq'
xbutil dump returns :

xbutil dump { "version": "1.1.0", "system": { "sysname": "Linux", "release": "5.4.0-xilinx-v2020.2", "version": "#1 SMP Tue Apr 5 07:41:01 UTC 2022", "machine": "aarch64", "glibc": "2.31", "linux": "PynqLinux, based on Ubuntu 20.04", "now": "Tue Apr 5 11:22:17 2022 GMT" }, "runtime": { "build": { "version": "2.8.0", "hash": "7c93966ead2dec777b92bdc379893f22b5bd561e", "date": "2022-04-05 07:54:25", "branch": "temp", "zocl": "2.8.0,7c93966ead2dec777b92bdc379893f22b5bd561e" } }, "board": { "info": { "dsa_name": "ZCU102", "vendor": "4334", "device": "65535", "subdevice": "65535", "subvendor": "65535", "xmcversion": "0", "ddr_size": "4294967296", "ddr_count": "1", "clock0": "100", "clock1": "0", "clock2": "0" }, "xclbin": { "uuid": "(null)" } } }

Hi,

Are you able to access JupyterLab from the browser?
If so, open a terminal within JupyterLab and try to launch your program.

You may also want to check if pynq was installed in the image.

Mario

Hello @marioruiz,

I was able to deploy successfully the cyber-security example, so I guess I have a working image :wink:

1 Like