Can’t rebuild the base overlay Pynq 2.7 - recipe for target 'hls_ip' failed

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1

Hello, everyone.

I am following A to make a base overlay of ZCU106 board, replacing ZCU104 base with ZCU106.

However, I got the following error.

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
bad lexical cast: source type value could not be interpreted as target
    while executing
"rdi::set_property core_revision 2204172212 {component component_1}"
    invoked from within
"set_property core_revision $Revision $core"
    (file "run_ippack.tcl" line 937)
INFO: [Common 17-206] Exiting Vivado at Sun Apr 17 22:12:52 2022...
ERROR: [IMPL 213-28] Failed to generate IP.
INFO: [HLS 200-111] Finished Command export_design CPU user time: 7.14 seconds. CPU system time: 0.54 seconds. Elapsed time: 16.22 seconds; current allocated memory: 315.719 MB.
command 'ap_source' returned error code
    while executing
"source color_convert_2/script.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

INFO: [HLS 200-112] Total CPU user time: 16.88 seconds. Total CPU system time: 1.16 seconds. Total elapsed time: 25.53 seconds; peak allocated memory: 311.841 MB.
INFO: [Common 17-206] Exiting vitis_hls at Sun Apr 17 22:13:02 2022...
child process exited abnormally
INFO: [Common 17-206] Exiting Vivado at Sun Apr 17 22:13:02 2022...
makefile:10: recipe for target 'hls_ip' failed
make: *** [hls_ip] Error 1

I’m using Vivado 2020.2 to match 2.7 version.
I also have a license for the zcu106 board.
Is there a solution to this problem?

2

Hi @jooeun526,

This looks like the 2KY22 bug https://support.xilinx.com/s/article/76960?language=en_US

Patch, re-clone the repo and rebuild.

Mario