PYNQ V2.7 SD image build fail for board PYNQ-Z2

[Willy]

Hi all,
I’m try to rebuild the Pynq v2.7 SD card image with following guide, but got errors:
https://pynq.readthedocs.io/en/v2.7.0/pynq_sd_card.html

Here are some my operations:

1. Setup a AMD host system with Ubuntut 20.04 64bit.
2. Download the Pynq V2.7 source code from github.
3. Use Vagrant to prepare Ubuntu OS
   3.1 The Vagran up help me to setup a VM with Ubuntu 18.04
   3.2 Install Vitis, Vivado, and Petalinux with related version on the location “/workspace/Xilinx”
   PYNQ V2.7, Xilinx Tool Version 2020.2, Petalinux version 2020.2
   3.3 Setup the appropriate setting for petalinux and vitis.
   I’m add these setting in bashrc file.

source /workspace/Xilinx/Vitis/2020.2/settings64.sh
source /workspace/Xilinx/Vivado/2020.2/settings64.sh
source /workspace/Xilinx/petalinux/settings.sh
petalinux-util --webtalk off

3.4 Also install petalinux necessary packages:
https://support.xilinx.com/s/article/73296?language=en_US
3.5 Switch shell to bash
sudo dpkg-reconfigure dash
4. Building the Image
4.1 cd /sdbuild/
4.2 make

After executing the make command, I will get below two different problems, and they seems happen randomly:
One for Vivado:

WARNING: [Vivado 12-8222] Failed run(s) : ‘pynqz2_ps7_0_synth_1’
wait_on_run: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:35 . Memory (MB): peak = 2623.246 ; gain = 0.000 ; free physical = 1992 ; free virtual = 2167
INFO: [Vivado 12-4895] Creating Hardware Platform: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2.xsa …
INFO: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated Hardware Platform.
WARNING: [Project 1-646] Board name, vendor and part not set in Hardware Platform.
WARNING: [Project 1-645] Board images not set in Hardware Platform.
INFO: [Hsi 55-2053] elapsed time for repository (/workspace/Xilinx/Vivado/2020.2/data/embeddedsw) loading 0 seconds
WARNING: [BD 41-2589] Platform should have atleast one axi memory mapped master interface. Enable a master AXI interface as platform AXI_PORT.
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 2623.246 ; gain = 0.000 ; free physical = 1209 ; free virtual = 2323
ERROR: [Common 17-70] Application Exception: Need an implemented design open to write bitstream. Aborting write_hw_platform…
INFO: [Common 17-206] Exiting Vivado at Tue May 24 20:06:35 2022…
makefile:13: recipe for target ‘bitstream’ failed
make[1]: *** [bitstream] Error 1
make[1]: Leaving directory ‘/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project’
Makefile:343: recipe for target ‘/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2020.2.bsp’ failed
make: *** [/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2020.2.bsp] Error 2

One for petalinux-build:

Built pynqz2 successfully!
make[1]: Leaving directory ‘/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project’

• cd /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp
• petalinux-create --type project --template zynq --name xilinx-pynqz2-2020.2
  INFO: Create project: xilinx-pynqz2-2020.2
  INFO: New project successfully created in /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2020.2
• cd xilinx-pynqz2-2020.2
• petalinux-config --get-hw-description=/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project --silentconfig
  INFO: Sourcing build tools
  INFO: Getting hardware description…
  INFO: Rename pynqz2.xsa to system.xsa
  [INFO] Generating Kconfig for project
  [INFO] Silentconfig project
  [INFO] Extracting yocto SDK to components/yocto
  ERROR: Failed to Extract Yocto SDK.
  ERROR: Failed to config project.
  ERROR: Get hw description Failed!.
  Makefile:343: recipe for target ‘/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2020.2.bsp’ failed
  make: *** [/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2020.2.bsp] Error 255

I also try to remove the build fails and rebuild with command:
make clean, make
or
make clean, make -B
The fail results are the same.

For the Vivado problem, I used Vivado GUI mode and open the XDC project in the build folder:
Run the bitstream generation, the result is PASS. I’m not sure what’s the reason…

For the peta-linux part, I check other posts in support forum but can’t find answer…

Below context is the Terminal in the VM during opening: I think my Vivado, Vitis, Petalinux should be installed correctly.

PetaLinux environment set to ‘/workspace/Xilinx/petalinux’
WARNING: This is not a supported OS
INFO: Checking free disk space
INFO: Checking installed tools
INFO: Checking installed development libraries
INFO: Checking network and other services
WARNING: No tftp server found - please refer to “UG1144 2020.2 PetaLinux Tools Documentation Reference Guide” for its impact and solution
INFO: Turn off webtalk feature!

[briansune]

Make sure your env is setup correctly:
https://discuss.pynq.io/t/stuck-at-extract-yocoto/4134/8?u=briansune

I had the same issue when building SD image on V2.7

Vagrant is not a good method to setup the SD build environment

[Willy]

@briansune
Thanks for your reply quickly.
I will try your way without using Vagrant…
Just want to confirm you final successful rebuilding the SD image for Pynq-Z2, right?

[briansune]

Of cause, 100% on AMD Intel Windows 10.
I also tried a lot of additional variations overlay and composable:

Composable:

PYNQ Composable c_dict issue

Great I guess the install Readme can add more info. Enclosing the install here: Install Script.ipynb (1.8 KB)

Power On bit load:

Boot overlay or bit load after power up

Cathal I humbly thank you but 1st I am not sure why you using 2.5 old revision here . 2nd had you tried the 2.7 boot.py and the differences between the flag is set or not? I already generate both w and wo the FPGA_MANAGER_${BOARD} flag case. And the result already discussed on above. There are so many case that the initial boot bit needed in example HDMI or RTOS applications. Meantime how slow the after boot load time it is? (if you had experience on 2.7 boot.py overlay) What I see from t…

Reduction of SD build wo generate all other boards:

Pynq 2.7 for Zybo-Z7

Hi Brian, I hope you’re doing great :-). Issues could be present as each time you run the Makefile, git makes changes locally. To make sure the build.sh file is getting modified, you should check the ~/PYNQ/sdbuild/build/ directory and search for the build.sh copied there. Lines after the 105 are not needed (since they are forcing the Pynq repo to be cloned again for the Pynq-Z2 and compile the original overlays). One workaround could be to just delete those lines by hand. I’m sorry I can’t gu…

[skalade]

Hi there,

At the top of the Vivado log there’s a peculiar message about synthesis failing…

@Willy

WARNING: [Vivado 12-8222] Failed run(s) : ‘pynqz2_ps7_0_synth_1’

Could you share the messages from before that, or if possible the full log?

Also, I highly recommend running make with the PYNQ_SDIST and PREBUILT flags using the board agnostic image.

Thanks
Shawn

[briansune]

That’s why ensure the ENV is install correct before even start.

There are so many unclear factors RAM not set enough CPU # is not enough causing such etc.

If the ENV is set properly there is no way build cannot pass. At least I ends up building all boards wo issue here.

This is completely expected when HDMI license are not included in some point when all the boards will generate no matter w / wo prebuild flag.

The make will automatically grep the head of the repository and i.e. build all as post suggested after line 105,165 can be remove accordingly.
I just lost interest on fixing the make script and post out here as 1st make fail you can goto the build project modify it and rebuild which the grep will inherently see it is exist and wo refresh it.

Pynq 2.7 for Zybo-Z7

Hi Brian, I hope you’re doing great :-). Issues could be present as each time you run the Makefile, git makes changes locally. To make sure the build.sh file is getting modified, you should check the ~/PYNQ/sdbuild/build/ directory and search for the build.sh copied there. Lines after the 105 are not needed (since they are forcing the Pynq repo to be cloned again for the Pynq-Z2 and compile the original overlays). One workaround could be to just delete those lines by hand. I’m sorry I can’t gu…

[Willy]

Hi Skalade,
Here you go:

/opt/qemu/bin/qemu-aarch64-static -version | fgrep 5.2.0
qemu-aarch64 version 5.2.0
/opt/qemu/bin/qemu-arm-static -version | fgrep 5.2.0
qemu-arm version 5.2.0
vivado -version | fgrep 2020.2
Vivado v2020.2.2 (64-bit)
vitis -version | fgrep 2020.2
****** Vitis v2020.2.2 (64-bit)
which petalinux-config
/workspace/Xilinx/petalinux/tools/common/petalinux/bin/petalinux-config
which arm-linux-gnueabihf-gcc
/workspace/Xilinx/Vitis/2020.2/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin/arm-linux-gnueabihf-gcc
which microblaze-xilinx-elf-gcc
/workspace/Xilinx/petalinux/tools/xsct/gnu/microblaze/lin/bin/microblaze-xilinx-elf-gcc
which ct-ng
/opt/crosstool-ng/bin/ct-ng
bash /pynq/sdbuild/scripts/check_env.sh
Checking system for required packages:
bc gperf bison flex texi2html texinfo help2man gawk libtool libtool-bin build-essential automake libglib2.0-dev device-tree-compiler qemu-user-static binfmt-support multistrap git lib32z1 libbz2-1.0 lib32stdc++6 libssl-dev kpartx zerofree u-boot-tools rpm2cpio libsdl1.2-dev rsync python3-pip gcc-multilib libidn11 curl libncurses5-dev lib32ncurses5
mkdir -p /pynq/sdbuild/build/Pynq-Z2
cp /pynq/sdbuild/boot/image_arm.its /pynq/sdbuild/build/Pynq-Z2/image.its
rm -rf /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp
mkdir -p /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp
BSP= BSP_BUILD=/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp BSP_ABS= BSP_PROJECT=xilinx-pynqz2-2020.2 /pynq/sdbuild/scripts/create_bsp.sh /pynq/sdbuild/../boards/Pynq-Z2 zynq
+ set -e
+ board=/pynq/sdbuild/../boards/Pynq-Z2
+ template=zynq
+ '[' -n '' ']'
+ cp -rf /pynq/sdbuild/../boards/Pynq-Z2/petalinux_bsp/hardware_project /pynq/sdbuild/../boards/Pynq-Z2/petalinux_bsp/meta-user /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp
+ cd /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project
+ '[' -e makefile ']'
+ make
make[1]: Entering directory '/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project'
vivado -mode batch -source pynqz2.tcl -notrace

****** Vivado v2020.2.2 (64-bit)
  **** SW Build 3118627 on Tue Feb  9 05:13:49 MST 2021
  **** IP Build 3115676 on Tue Feb  9 10:48:11 MST 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source pynqz2.tcl -notrace
INFO: [BD::TCL 103-2003] Currently there is no design <pynqz2> in project, so creating one...
Wrote  : </pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/pynqz2.bd> 
INFO: [BD::TCL 103-2004] Making design <pynqz2> as current_bd_design.
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "pynqz2".
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:  
xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:xlconcat:2.1  .
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values. 
Wrote  : </pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/pynqz2.bd> 
INFO: [Common 17-206] Exiting Vivado at Tue May 24 20:04:44 2022...
vivado -mode batch -source build_bitstream.tcl -notrace

****** Vivado v2020.2.2 (64-bit)
  **** SW Build 3118627 on Tue Feb  9 05:13:49 MST 2021
  **** IP Build 3115676 on Tue Feb  9 10:48:11 MST 2021
    ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

source build_bitstream.tcl -notrace
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/workspace/Xilinx/Vivado/2020.2/data/ip'.
Reading block design file </pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/pynqz2.bd>...
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - ps7
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk1
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk2
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk3
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Successfully read diagram <pynqz2> from block design file <./pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/pynqz2.bd>
INFO: [BD 41-1662] The design 'pynqz2.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/synth/pynqz2.v
VHDL Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/sim/pynqz2.v
VHDL Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/hdl/pynqz2_wrapper.v
INFO: [Project 1-1716] Could not find the wrapper file ./pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/hdl/pynqz2_wrapper.v, checking in project .gen location instead.
INFO: [Vivado 12-12390] Found file ./pynqz2/pynqz2.gen/sources_1/bd/pynqz2/hdl/pynqz2_wrapper.v, adding it to Project
INFO: [BD 41-1662] The design 'pynqz2.bd' is already validated. Therefore parameter propagation will not be re-run.
VHDL Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/synth/pynqz2.v
VHDL Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/sim/pynqz2.v
VHDL Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/hdl/pynqz2_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
Exporting to file /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/hw_handoff/pynqz2.hwh
Generated Block Design Tcl file /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/hw_handoff/pynqz2_bd.tcl
Generated Hardware Definition File /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/synth/pynqz2.hwdef
INFO: [IP_Flow 19-7066] Running IP cache check for IP pynqz2_ps7_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP pynqz2_rst_ps7_0_fclk0_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP pynqz2_rst_ps7_0_fclk1_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP pynqz2_rst_ps7_0_fclk2_0
INFO: [IP_Flow 19-7066] Running IP cache check for IP pynqz2_rst_ps7_0_fclk3_0
[Tue May 24 20:05:32 2022] Launched pynqz2_ps7_0_synth_1, pynqz2_rst_ps7_0_fclk0_0_synth_1, pynqz2_rst_ps7_0_fclk1_0_synth_1, pynqz2_rst_ps7_0_fclk2_0_synth_1, pynqz2_rst_ps7_0_fclk3_0_synth_1, synth_1...
Run output will be captured here:
pynqz2_ps7_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_ps7_0_synth_1/runme.log
pynqz2_rst_ps7_0_fclk0_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_rst_ps7_0_fclk0_0_synth_1/runme.log
pynqz2_rst_ps7_0_fclk1_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_rst_ps7_0_fclk1_0_synth_1/runme.log
pynqz2_rst_ps7_0_fclk2_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_rst_ps7_0_fclk2_0_synth_1/runme.log
pynqz2_rst_ps7_0_fclk3_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_rst_ps7_0_fclk3_0_synth_1/runme.log
synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/synth_1/runme.log
[Tue May 24 20:05:32 2022] Launched impl_1...
Run output will be captured here: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 2623.246 ; gain = 120.055 ; free physical = 4584 ; free virtual = 5843
[Tue May 24 20:05:32 2022] Waiting for impl_1 to finish...
[Tue May 24 20:06:07 2022] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'pynqz2_ps7_0_synth_1'
wait_on_run: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:35 . Memory (MB): peak = 2623.246 ; gain = 0.000 ; free physical = 1992 ; free virtual = 2167
INFO: [Vivado 12-4895] Creating Hardware Platform: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2.xsa ...
INFO: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated Hardware Platform.
WARNING: [Project 1-646] Board name, vendor and part not set in Hardware Platform.
WARNING: [Project 1-645] Board images not set in Hardware Platform.
INFO: [Hsi 55-2053] elapsed time for repository (/workspace/Xilinx/Vivado/2020.2/data/embeddedsw) loading 0 seconds
WARNING: [BD 41-2589] Platform should have atleast one axi memory mapped master interface. Enable a master AXI interface as platform AXI_PORT.
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:00:17 ; elapsed = 00:00:24 . Memory (MB): peak = 2623.246 ; gain = 0.000 ; free physical = 1209 ; free virtual = 2323
ERROR: [Common 17-70] Application Exception: Need an implemented design open to write bitstream. Aborting write_hw_platform..
INFO: [Common 17-206] Exiting Vivado at Tue May 24 20:06:35 2022...
makefile:13: recipe for target 'bitstream' failed
make[1]: *** [bitstream] Error 1
make[1]: Leaving directory '/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project'
Makefile:343: recipe for target '/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2020.2.bsp' failed
make: *** [/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2020.2.bsp] Error 2

[briansune]

Here is the solution:

Novel Issues: Quick Porting of PYNQ using Pre-built images

So the ENV setup following my steps are working? From my experience the name of the xsa dont matter as it will rename it if it is unique on the folder. PREBUILT=/media/sf_ZC706_shared/focal.arm.2.7.0_2021_11_17.tar.gz For this don’t put this is the sharing folder right might lead to issue as well. Move to location home and rerun again. $(BUILD_ROOT)/PYNQ/build.sh remove line started @105 to 165 to reduce the build of other unnecessary board and licensing issue. Try make with the same set…

[Willy]

Hi briansune,
I re-setup the VM according to the your post: Stuck at extract yocoto - #8 by briansune
But I still get the same problem…

Do you have any suggestion about this problem??

[briansune]

Do you PS and kill all background process?
And did you use prebuild as well?

Manually open the Vivado project and reset the project and make again and see this is still problematic.

[Willy]

I’m try to restart the VM, but the result is the same.
Sorry, I’m not very understand what you mean about the prebuild.
I clone the git code as you point out and chmod 777 for it without other modification.
Switch to the PYNQ/sdbuild, and execute “make”, and then get the error message.

[briansune]

Meantime my instruction had additional update at below did you see those as well (just make sure).

https://pynq.readthedocs.io/en/latest/pynq_sd_card.html

@ Building the Image
cd /sdbuild/
make PREBUILT= BOARDS=

Download the image from here:

PYNQ - Python productivity for Zynq

Remember dont put this file in share location.

[Willy]

I also use Vivado GUI to open the building project “/home/willy/PYNQ/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.xpr”.
If I manually click the “Run Implementation” button, the project can pass the process.

[briansune]

so you just need to close it and back to sdbuild folder run the
make PREBUILT= BOARDS=
again it will pass if this is the case
make sure you remove the line on the build.sh as the above post

PYNQ V2.7 SD image build fail for board PYNQ-Z2

Here is the solution:

[Willy]

Sorry, what parameter for the PREBUILT I should put?
I guess I need to download the “PYNQ rootfs aarch64 v2.7” and include the path for parameter of PREBUILT.

[briansune]

[Willy]

1. Remove line 105~165 in the PYNQ/build.sh
2. Download the prebuilt board-agnostic image
3. Execute command: make PREBUILT=focal.aarch64.2.7.0_2021_11_17.tar.gz BOARDS=Pynq-Z2

The error still happen again:

[briansune]

Did you make clean?
If so you dont need to do so as it the make will grep the head of the git.
And did you clean the build in the Vivado?

[Willy]

Yes, I make clean.
If I don’t do that, the following error will appear:
ERROR: [Common 17-53] User Exception: Project already exists on disk, please use ‘-force’ option to overwrite:
/home/willy/PYNQ/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.xpr
/home/willy/PYNQ/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs
/home/willy/PYNQ/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.srcs
/home/willy/PYNQ/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.cache
/home/willy/PYNQ/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.hw
/home/willy/PYNQ/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.ip_user_files
/home/willy/PYNQ/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen
INFO: [Common 17-206] Exiting Vivado at Tue May 31 16:59:52 2022…
makefile:10: recipe for target ‘block_design’ failed

I’m not do the clear build in Vivado GUI, I just click the “generate bitstream” button for a try.
I had removed the line 105~165 in the PYNQ/build.sh, is it corrected?

[briansune]

first the modify file should located in:

If you clean the build it will just grep the git head and override and build all boards.
Second the tcl script will generate the project for you so try remove the folder pynqz2 in /home/willy/PYNQ/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/