vagrant@ubuntu-bionic:/pynq/sdbuild$ make BOARDS=Pynq-Z2
/opt/qemu/bin/qemu-arm-static -version | fgrep 5.2.0
qemu-arm version 5.2.0
vivado -version | fgrep 2022.1
Vivado v2022.1 (64-bit)
vitis -version | fgrep 2022.1
****** Vitis v2022.1 (64-bit)
which petalinux-config
/workspace/Xilinx/PetaLinux/2022.1/tool/tools/common/petalinux/bin/petalinux-config
which arm-linux-gnueabihf-gcc
/workspace/Xilinx/Vitis/2022.1/gnu/aarch32/lin/gcc-arm-linux-gnueabi/bin/arm-linux-gnueabihf-gcc
which microblaze-xilinx-elf-gcc
/workspace/Xilinx/PetaLinux/2022.1/tool/tools/xsct/gnu/microblaze/lin/bin/microblaze-xilinx-elf-gcc
which ct-ng
/opt/crosstool-ng/bin/ct-ng
bash /pynq/sdbuild/scripts/check_env.sh
Checking system for required packages:
bc gperf bison flex texi2html texinfo help2man gawk libtool libtool-bin build-essential automake libglib2.0-dev device-tree-compiler qemu-user-static binfmt-support multistrap git lib32z1 libbz2-1.0 lib32stdc++6 libssl-dev kpartx zerofree u-boot-tools rpm2cpio libsdl1.2-dev rsync python3-pip gcc-multilib libidn11 curl libncurses5-dev lib32ncurses5
mkdir -p /pynq/sdbuild/build/Pynq-Z2
cp /pynq/sdbuild/boot/image_arm.its /pynq/sdbuild/build/Pynq-Z2/image.its
rm -rf /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp
mkdir -p /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp
BSP= BSP_BUILD=/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp BSP_ABS= BSP_PROJECT=xilinx-pynqz2-2022.1 /pynq/sdbuild/scripts/create_bsp.sh /pynq/sdbuild/../boards/Pynq-Z2 zynq
+ set -e
+ board=/pynq/sdbuild/../boards/Pynq-Z2
+ template=zynq
+ '[' -n '' ']'
+ cp -rf /pynq/sdbuild/../boards/Pynq-Z2/petalinux_bsp/hardware_project /pynq/sdbuild/../boards/Pynq-Z2/petalinux_bsp/meta-user /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp
+ cd /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project
+ '[' -e makefile ']'
+ make
make[1]: Entering directory '/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project'
vivado -mode batch -source pynqz2.tcl -notrace
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source pynqz2.tcl -notrace
INFO: [BD::TCL 103-2003] Currently there is no design <pynqz2> in project, so creating one...
Wrote : </pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/pynqz2.bd>
INFO: [BD::TCL 103-2004] Making design <pynqz2> as current_bd_design.
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "pynqz2".
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:
xilinx.com:ip:processing_system7:5.5 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:xlconcat:2.1 .
CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-1] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values.
CRITICAL WARNING: [PSU-2] Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.033 . PS DDR interfaces might fail when entering negative DQS skew values.
WARNING: [BD 5-700] No address spaces matched 'get_bd_addr_spaces -of_objects /ps7 -filter {path == /ps7/Data}'
WARNING: [BD 5-699] No address segments matched 'get_bd_addr_segs -of_objects {}'
Wrote : </pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/pynqz2.bd>
INFO: [Common 17-206] Exiting Vivado at Mon Jan 15 18:54:45 2024...
vivado -mode batch -source build_bitstream.tcl -notrace
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source build_bitstream.tcl -notrace
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/workspace/Xilinx/Vivado/2022.1/data/ip'.
Reading block design file </pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/pynqz2.bd>...
Adding component instance block -- xilinx.com:ip:processing_system7:5.5 - ps7
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk0
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk1
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk2
Adding component instance block -- xilinx.com:ip:proc_sys_reset:5.0 - rst_ps7_0_fclk3
Adding component instance block -- xilinx.com:ip:xlconcat:2.1 - xlconcat_0
Successfully read diagram <pynqz2> from block design file <./pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/pynqz2.bd>
INFO: [BD 41-1662] The design 'pynqz2.bd' is already validated. Therefore parameter propagation will not be re-run.
Verilog Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/synth/pynqz2.v
Verilog Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/sim/pynqz2.v
Verilog Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/hdl/pynqz2_wrapper.v
INFO: [Project 1-1716] Could not find the wrapper file ./pynqz2/pynqz2.srcs/sources_1/bd/pynqz2/hdl/pynqz2_wrapper.v, checking in project .gen location instead.
INFO: [Vivado 12-12390] Found file ./pynqz2/pynqz2.gen/sources_1/bd/pynqz2/hdl/pynqz2_wrapper.v, adding it to Project
INFO: [BD 41-1662] The design 'pynqz2.bd' is already validated. Therefore parameter propagation will not be re-run.
Verilog Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/synth/pynqz2.v
Verilog Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/sim/pynqz2.v
Verilog Output written to : /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/hdl/pynqz2_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block ps7 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block rst_ps7_0_fclk3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block xlconcat_0 .
Exporting to file /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/hw_handoff/pynqz2.hwh
Generated Hardware Definition File /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.gen/sources_1/bd/pynqz2/synth/pynqz2.hwdef
[Mon Jan 15 18:55:25 2024] Launched pynqz2_rst_ps7_0_fclk3_0_synth_1, pynqz2_rst_ps7_0_fclk2_0_synth_1, pynqz2_rst_ps7_0_fclk1_0_synth_1, pynqz2_rst_ps7_0_fclk0_0_synth_1, pynqz2_ps7_0_synth_1, synth_1...
Run output will be captured here:
pynqz2_rst_ps7_0_fclk3_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_rst_ps7_0_fclk3_0_synth_1/runme.log
pynqz2_rst_ps7_0_fclk2_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_rst_ps7_0_fclk2_0_synth_1/runme.log
pynqz2_rst_ps7_0_fclk1_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_rst_ps7_0_fclk1_0_synth_1/runme.log
pynqz2_rst_ps7_0_fclk0_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_rst_ps7_0_fclk0_0_synth_1/runme.log
pynqz2_ps7_0_synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/pynqz2_ps7_0_synth_1/runme.log
synth_1: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/synth_1/runme.log
[Mon Jan 15 18:55:25 2024] Launched impl_1...
Run output will be captured here: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2/pynqz2.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:15 ; elapsed = 00:00:19 . Memory (MB): peak = 2730.828 ; gain = 32.016 ; free physical = 4389 ; free virtual = 5973
[Mon Jan 15 18:55:25 2024] Waiting for impl_1 to finish...
[Mon Jan 15 18:56:43 2024] impl_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'pynqz2_rst_ps7_0_fclk3_0_synth_1', 'pynqz2_rst_ps7_0_fclk2_0_synth_1'
wait_on_runs: Time (s): cpu = 00:00:00 ; elapsed = 00:01:18 . Memory (MB): peak = 2730.828 ; gain = 0.000 ; free physical = 3465 ; free virtual = 3772
INFO: [Project 1-1937] No bit file available for '-include_bit'. To use this feature, run implementation through write_bitstream and then re-run write_hw_platform with '-include_bit'
INFO: [Project 1-1918] Creating Hardware Platform: /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project/pynqz2.xsa ...
INFO: [Project 1-655] Project does not have Board Part set. Board related data may be missing or incomplete in the generated Hardware Platform.
WARNING: [Project 1-646] Board name, vendor and part not set in Hardware Platform.
WARNING: [Project 1-645] Board images not set in Hardware Platform.
INFO: [Project 1-1906] Skipping semantic label enumeration.
WARNING: [BD 41-2589] Platform should have atleast one axi memory mapped master interface. Enable a master AXI interface as platform AXI_PORT.
INFO: [PFM-62] PFM.AXI_PORT for ps7/M_AXI_GP0 does not have an sptag specified, so is being assigned an auto generated name of GP
INFO: [PFM-62] PFM.AXI_PORT for ps7/M_AXI_GP1 does not have an sptag specified, so is being assigned an auto generated name of GP
INFO: [PFM-62] PFM.AXI_PORT for ps7/S_AXI_ACP does not have an sptag specified, so is being assigned an auto generated name of ACP
INFO: [PFM-62] PFM.AXI_PORT for ps7/S_AXI_HP0 does not have an sptag specified, so is being assigned an auto generated name of HP
INFO: [PFM-62] PFM.AXI_PORT for ps7/S_AXI_HP1 does not have an sptag specified, so is being assigned an auto generated name of HP
INFO: [PFM-62] PFM.AXI_PORT for ps7/S_AXI_HP2 does not have an sptag specified, so is being assigned an auto generated name of HP
INFO: [PFM-62] PFM.AXI_PORT for ps7/S_AXI_HP3 does not have an sptag specified, so is being assigned an auto generated name of HP
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In0 does not have an assigned id. It is being assigned ID 1.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In1 does not have an assigned id. It is being assigned ID 0.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In2 does not have an assigned id. It is being assigned ID 2.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In3 does not have an assigned id. It is being assigned ID 3.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In4 does not have an assigned id. It is being assigned ID 4.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In5 does not have an assigned id. It is being assigned ID 5.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In6 does not have an assigned id. It is being assigned ID 6.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In7 does not have an assigned id. It is being assigned ID 7.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In8 does not have an assigned id. It is being assigned ID 8.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In9 does not have an assigned id. It is being assigned ID 9.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In10 does not have an assigned id. It is being assigned ID 10.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In11 does not have an assigned id. It is being assigned ID 11.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In12 does not have an assigned id. It is being assigned ID 12.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In13 does not have an assigned id. It is being assigned ID 13.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In14 does not have an assigned id. It is being assigned ID 14.
CRITICAL WARNING: [PFM-48] Interrupt pin /xlconcat_0/In15 does not have an assigned id. It is being assigned ID 15.
INFO: [Project 1-1042] Successfully generated hpfm file
write_project_tcl: Time (s): cpu = 00:00:13 ; elapsed = 00:00:24 . Memory (MB): peak = 2738.859 ; gain = 8.031 ; free physical = 2927 ; free virtual = 3897
INFO: [Hsi 55-2053] elapsed time for repository (/workspace/Xilinx/Vivado/2022.1/data/embeddedsw) loading 7 seconds
ERROR: [Common 17-69] Command failed: Need an implemented design open to write bitstream. Aborting write_hw_platform..
INFO: [Common 17-206] Exiting Vivado at Mon Jan 15 18:57:41 2024...
makefile:16: recipe for target 'bitstream' failed
make[1]: *** [bitstream] Error 1
make[1]: Leaving directory '/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/hardware_project'
Makefile:371: recipe for target '/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2022.1.bsp' failed
make: *** [/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2022.1.bsp] Error 2
Where problem could be?
I will very appreciate it if someone help me.
Ok, now I see that in one of log files there are error:
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2623.215 ; gain = 0.000 ; free physical = 456 ; free virtual = 1275
INFO: [Netlist 29-17] Analyzing 13 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
Parent process (pid 10299) has died. This helper process will now exit
/workspace/Xilinx/Vivado/2022.1/bin/loader: line 312: 10299 Killed "$RDI_PROG" "$@"
terminate called after throwing an instance of 'std::bad_alloc'
what(): std::bad_alloc
/workspace/Xilinx/Vivado/2022.1/bin/loader: line 312: 10515 Aborted (core dumped) "$RDI_PROG" "$@"
I will try to increase VM memory size. I didn’t change any defaults, using steps provided in docs.
...
*
* User Layers
*
user layer 0 (USER_LAYER_0) [] (NEW)
#
# configuration written to /pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2022.1/project-spec/configs/config
#
[INFO] Extracting yocto SDK to components/yocto. This may take time!
PetaLinux Extensible SDK installer version 2022.1
=================================================
You are about to install the SDK to "/pynq/sdbuild/build/Pynq-Z2/petalinux_bsp/xilinx-pynqz2-2022.1/components/yocto". Proceed [Y/n]? Y
Extracting SDK...tar: ./layers/core/scripts/pybootchartgui/pybootchartgui/main.py: Cannot hard link to ‘./layers/core/scripts/pybootchartgui/pybootchartgui/main.py.in’: Operation not permitted
tar: ./layers/core/bitbake/bin/bitbake-dumpsig: Cannot hard link to ‘./layers/core/bitbake/bin/bitbake-diffsigs’: Operation not permitted
...tar: Exiting with failure status due to previous errors
ERROR: Failed to Extract Yocto SDK.
also side question, is it possible to rerun make, without cleaning all project? because I got file exists error, and I need to run make clean, despite previous make steps were successful and error was only in last step.
The shared folders provide a minimal file system to allow exchange of files between the host and guest. With the VBoxManage command you have used you can now create symbolic links (ln -s) but hard links (ln) are not supported.
Wondering how you guys are building Pynq while “official” vagrant method gives so many errors
