PYNQ-ZU - Could not find IP or hierarchy xfft in overlay

[LightwishWONG]

Hi everyone,
I’m trying to use PYNQ-ZU board to run FFT. I followed the step-by-step guide provided by xilinx here. The pdf guide is here. After I finished the block design in vivado and ran synthesis, I uploaded the .bit file, the .tcl file and the .hwh file to the PYNQ-ZU board and imported the FFT overlay in a jupyter notebook. But the fft IP could not be found, while other IPs like dma and fifo could be detected successfully, as shown below.

If I checked the fft IP specifically, it came an error.

The block design created in vivado is shown below. I think maybe something is wrong there but I can’t figure it out.

I use PYNQ-ZU with image v2.6 and vivado 2020.1. Need to mention that in the step-by-step guide here, the author uses PYNQ-Z1 board. So in the guide the zynq PS IP in the block design (zynq) is different from that in my block design (zynq UltraScale). Some ports may be different, like IRQF2P port in zynq IP while pl_ps_irq port in zynq UltraScale IP. Could this be the problem?

Please help me fix it. Many thanks!

[marioruiz]

Hi @LightwishWONG,

Welcome to our community.
The ip_dict only shows memory-mapped IP, with an AXI4-Lite interface. The xfft you have in your design is not memory mapped, and the streaming interface is connected to a DMA

You can learn how to move data to this IP by following Cathal’s tutorial.

Tutorial: PYNQ DMA (Part 1: Hardware design)

PYNQ DMA tutorial (Part 1: Hardware design) This tutorial will show you how to use the Xilinx AXI DMA with PYNQ. It will cover adding the AXI DMA to a new Vivado hardware design and show how the DMA can be controlled from PYNQ. This tutorial is based on the v2.6 PYNQ image and will use Vivado 2020.1. If you are using a different PYNQ version you should be able to follow the same steps in this tutorial, but you should make sure you are using the supported version of Vivado for that PYNQ release. …

Mario

[LightwishWONG]

Hi @marioruiz ,
Thanks for your kind help. I’ll follow this tutorial.

[LightwishWONG]

I’ve learned this tutorial. I think in my block design the xfft and the DMA are just connected as described in the tutorial you provide, as shown below.

The connection between the DMA and the zynq UltraScale+ is shown below

Now I’m still confused how to move data to the xfft IP.

[marioruiz]

Hi,

Part 2 of the tutorial covers the software part. You may also want to read the documentation for the DMA

https://pynq.readthedocs.io/en/latest/pynq_libraries/dma.html

https://pynq.readthedocs.io/en/latest/overlay_design_methodology/pspl_interface.html

Mario

[LightwishWONG]

Hi,

I’ve learned part 2 as well. Do you mean that is actually not a hardware problem and what I should do now is to write some code to make the xfft IP mamory mapped?

[marioruiz]

No, you need to move the data via the DMA. The xfft IP only accepts samples via AXI4-Stream. This data movement is going to be very similar to the way Cathal moves data in the tutorial.

Mario

[briansune]

@LightwishWONG

Hello Wong,

Just from what I experienced in before about DFT IP had a simulation issue on Vivado 2020.2.
I am not sure about FFT but short search also see a lot of issue and path so paid a bit attention to the patch is handy.
See issue about DFT here
Ensure you had patch the DFT as well on Vivado 2020.2 IP if you need to use that.

Bests

[LightwishWONG]

Hi Mario,

Sorry I haven’t replied for so long. Lately I’ve been busy with another project. The tutorial you recommend made by Cathal is really great, which explains the details thoroughly. As you said before, the key is how to transfer and receive data using DMA. Now I successfully run the hardware FFT. Many thanks for your kind help!