PYNQ-Z2 board JTAG jumper link query

Hi @cathalmccabe ,

I looked at the following PYNQ-Z2 user manual and could not see anything mentioned about the 4 pin jumper link (ie the 2nd horizontal 4 pin (is that JP2?) that lists on the far left end PLL and on the far right end JTAG) that is exactly positioned below the boot mode jumper JP1? (1st horizontal 4 pin).

Currently just used the top horizontal 1st 4 pin (SD/QSPI/JTAG) in MicroSD mode successfully by placing the jumper link to the far left to select booting via MicroSD mode.

Wrt also the board layout Image-5 :

this shows all 8 pins for boot mode selection. This is confusing !

If I want to set the boot jumper to JTAG to download code to the board my thought was just to place the jumper link to the 1st horizontal 4 pin (JP1) far right end to select the JTAG mode.

BUT what about the JTAG displayed on the bottom 4 pin (PLL / JTAG) ie I think that is JP2 ? of the PYNQ-Z2 board? What is that JTAG mode used for? Is that for something else ?


Seen in PYNQ-Z1 documentation the following :

“The PYNQ-Z1 is configured to boot in Cascaded JTAG mode, which allows the PS to be accessed via the same JTAG port as the PL. It is also possible to boot the PYNQ-Z1 in Independent JTAG mode by loading a jumper in JP2 and shorting it. This will cause the PS to not be accessible from the onboard JTAG circuitry, and only the PL will be visible in the scan chain. To access the PS over JTAG while in independent JTAG mode, users will have to route the signals for the PJTAG peripheral over EMIO, and use an external device to communicate with it”

So in PYNQ-Z1 board JP2 could be setup in independent JTAG mode to cause PS not to be accessible from the onboard JTAG circuitry and only the PL to be visible in the scan chain. Is this the same behaviour for the PYNQ-Z2 JP2 (in JTAG mode) ?

Your prompt reply to this matter will be appreciated.

I would recommend to look at Pages 153-154 of Zynq-7000 TRM (UG585). The 2nd header allows independent JTAG access to PL, if desired.