As a follow up… I managed to recreate and validate the previously mentioned DPR design in Vivado 2022.2 without issues. The partial bitstream generation is correct and the design work as expected using PYNQ 3.0.1 Image.
Vivado 2022.1 Partial Bitstream File Information:
Xilinx BIT data - from BD_wrapper;UserID=0XFFFFFFFF;PARTIAL=TRUE;Version=2022.1 - for 7z020clg400 - built 2023/06/13(12:10:12) - data length 0xb8
Vivado 2022.2 Partial Bitstream File Information:
Xilinx BIT data - from BD_wrapper;UserID=0XFFFFFFFF;PARTIAL=TRUE;Version=2022.2 - for 7z020clg400 - built 2023/06/12(15:58:00) - data length 0x167b9c
This is not a PYNQ issue and it is mostly related to DPR designs with ZYNQ-7000 on Vivado 2022.1.