Hello all,
Introduction
Due to limited support on the modulator(s) about example of DFX and procedure.
I will try to share the DFX on PYNQ 2.7 flow and method that I think it is working.
The goal is to provide a simplest and easiest start of DFX on PR.
No “composite overlay”, no other installation just PYNQ default API.
First we are targeting Vivado 2020.2 not 2020.2.# which is the same build revision of the PYNQ on SD Image.
So the first element is to make sure it is aligning both SD image build environment.
There are many concerns why DFX is having hard time on 2020.2 is because Xilinx introduce BDC after 2020 version.
Design
Step 1. HLS IP for the PR-Block
Both the AXI-Stream HLS IP will be attached via GitHub:
Step 2. Vivado Project
As usually, we are going build the project. However we will stop at the stage of synthesis and run tcl command afterward.
The overall block images are shown below:
As for the PR section:
After the first PR-IP is synthesized:
We will open the synthesis design and start series of TCL command to generate the required bitstream and block-box to hold our PR-Block design.
A: We will save one of the full design cell that we are going to PR.
Remember to change to current working directory before start.
It will be nicer to make a folder to hold these check point as well.
In the below path_to_cell, please see the left hierarchy and see the name and layer.
write_checkpoint -cell pr_example_i/pr_sec/pr_sub_0 sub_cell.dcp
B: Change the sub IP to add and synthesis again
Once the synthesis is completed, we will open the Synthesis Design and save the checkpoint as (a) had shown.
write_checkpoint -cell pr_example_i/pr_sec/pr_add_0 add_cell.dcp
C: Modify the cell to a reconfigurable cell via GUI (easier)
Press the + sign to add properties.
Check the checker box to enable the function.
And make sure the DONT TOUCH checker box is activated (if this cannot be seen in the list add to see).
d: Assign P-Block via right click on cell.
Now we are going to floor-plan the Cell that can be configured.
Make sure the P-Block reset and snapping is set as shown:
After assign the section, we will undergo a DRC to make sure things is good.
Goto Report and run DRC:
E: DC - Design Compile
Back to tcl command window and run the follow commands:
opt_design
place_design
route_design
Once the DC flow is completed, we will make a check point.
write_checkpoint pr_add.dcp
F: Change the current design to a black-box and load other PR design.
update_design -cell pr_example_i/pr_sec/pr_add_0 -blackbox
lock_design -level routing
As we can see the orange color represent the design locked while the BB is now ready to reload other design.
Make a check point to reserve for future usage.
write_checkpoint pr_bb.dcp
F: Load previous SUB IP back to the BB
read_checkpoint -cell pr_example_i/pr_sec/pr_add_0 ./sub_cell.dcp
Follow Step E to DC.
After DC, write the check point as pr_sub.dcp
G: Verify and compare the PR design over different variants
To ensure the loaded design to the BB is correct preform a verification
pr_verify -initial pr_sub.dcp -additional pr_add.dcp
H: Export Bit-Stream
Open each check point via tcl command window:
open_checkpoint pr_add.dcp
write_bitstream -file pr_add.bit
We should see 1 base bit-stream along with a partial bitstream for the PR-Block.
open_checkpoint pr_sub.dcp
write_bitstream -file pr_sub.bit
Now we are all set. Ready to turn on the PYNQ board to transfer these files.
Script and PYNQ Setup
Now we will need the hwh and one of the full bit-stream either pr_add or pr_sub as the core are the same.
We are going to renaming a bit for better reading, for the pr_add/pr_sub.bit → pr_full.bit along with the hwh.
As for the pr-bit-stream as shown below:
First we loaded a sub PR:
Now we try out a add PR:
Wonderful, we can reprogram the PL wo touching the other PL fixed design.
Enjoy~ =]
