PYNQ 2.7 DFX Partial Reconfiguration under Vivado 2020.2 - TCL Script ALL-IN-ONE

Hello All,

Hope you all ENJOY~
Due to lots of users and developers are not familiar the differences between diamond zip and block-based PR design before 2022.x Vivado.

I am going to explain and make a follow up tutorial:

The MAJOR different of block and pure RTL designs:
Block based design cannot use BDC ← so you can only use tcl command to run the reconfiguration flow and general Vivado run processes is good up to synthesis, afterward manual tcl command for implementations and bit generation.

I am enclosing a TCL all-in-one project create and bit generation script here:

Make sure to edit the path accordingly!!
All you need is open vivado and cd to the project folder you plan to setup.
As for the ZYNQ block preset info you can prepare in other project and renamed as base_overlay_dfx.tcl

source dfx_project.tcl

base_overlay_dfx.tcl (38.0 KB)
dfx_project.tcl (9.3 KB)
pl_led.v (815 Bytes)

The test sub and add IP:

All you need in a folder is these files:


After execute the TCL script, there will be couples of bit files. Just follow the final parts of the 1st tutorial and you can try out how PR can be done in PYNQ + Vivado TCL.

As always ENJOY~

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Thanks for your guidence. You showthat i need a “top.xdc”. But I can’t find it in the document you provided. How can I get it?

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XDC is just for constraining the I/O of the FPGA you are using, this means it will be differ from users. So there are no points to share out when it is just trying to map to LEDs and also this is a very good point for user to double check if the FPGA series they had select is correct when 900 BGA vs 400BGA, some IO might not even exist.

Meanwhile, I forgot if there are any external oscillator is used in this example. If no then the timing constrains are not even critical.

So I cannot see why top.xdc will be a big problem. As long as you understand what that file really try to do.