PYNQ-Z2 DFX Issues with Vivado 2022.1

[briansune]

@mendes-davi

I do saw someone in this forum working around BDC on DFX designs

Adding Reconfigurable Modules to Partitions in the Composable Pipeline Design

Hi all, I am currently looking into adding an IP from the Vitis Vision library into one of the dfx regions of the composable overlay design and synthesising it using the Abstract Shell methodology. The Xilinx guides on how to do so are very clear and straightforward, however, I have some queries as to how to adapt the procedure for the composable overlay design. First I understand I need to add a Reconfigurable Module (RM) using the DFX wizard, however, when I attempt to do so I get greeted wi…

What this post had mentioned is BDC could introduce longer regenerate time which abstract method is a better.

However, myself applications and task never involve real room for DFX unless only study and try around behavior. When using FPGA, most cases are testing / R&D purpose, which FPGA is far optimal for large volume product design. =[ over-cost (something like S6+A53 CPU overrun the cost many times)

ENJOY~