PYNQ: PYTHON PRODUCTIVITY

Random number generator

I have a Pynq Z1 and have tested out a couple of the default overlays in python, e.g. boolean_generator, pattern_generator, etc. (Just basic tutorials from https://pynq.readthedocs.io/en/latest/index.html)

However, I’m wondering if the pre-built image found here: http://www.pynq.io/board.html
includes an overlay(s) that can be used for (pseudo) random number generator? I.e. so one does not have to develop an IP, HLS, whatever the names.

I find it amazing that the information regarding a random number generation using pynq is, except scarce, targeting only people understanding all this IP, HLS, Axiic etc. No “layman” guidelines.

No development using existing bitstreams/overlays with the pynq python interface is too complex, but I lack any kind of knowledge of developing bitstreams myself. Vivado, mivado, etc.are foreign languages.

Please help.

No, there isn’t an existing overlay that I’m aware of to do this.

This is a very specific request. I’m not sure why you expect that this would be available.

What exactly are you trying to do? Could you just use a software random number generator?

Cathal

It’s seems such an “easy”/straightforward thing to implement, I mean for HW developers… some ring oscillator, LSFR etc haha, I don’t know.

Sure, I could implement a sw random nr generator, but I’m going to use the software (OS) for other resources as well. I want to let the fpga run the random number generator in it’s own domain without having to split resources with other OS processes and since speed will be of the essence I don’t want it being limited by be OS CPU.

Does that make sense?

I asked exactly what you need to do as if you only need a single pseudo random number, you could run rand() once in Python and then you are done.

Cathal

I need to generate random numbers continuously as fast as possible and connect the different outcomes to physical outputs.

Using rand() in python under a while(True) loop will eat up all OS resources and still not be as fast at the FPGA