PYNQ: PYTHON PRODUCTIVITY FOR ZYNQ

Toolchains for simple Verilog on PYNQ board?

Hi. I’m new to FPGAs, so apologies for the simplicity (and ignorance) of this question. While many developers may use the overlays for creating applications, I’m interesting in low-level Verilog programming in order build and test simple circuits like the ones in this paper: Experiments on autonomous Boolean networks. For example, see the very short snippet of Verilog code on page 2.

module my_osc(s_in,s_out);
   wire [20:0] delay /*synthesis keep*/;
   assign delay[0] = delay[20] | s_in;
   assign delay[1] = ~delay[0];
   ...
   assign delay[20] = ~delay[19];
   assign s_out = delay[20];
endmodule

I’d also like to implement circuits with simple input/output, like in Figure 2 of this paper: Reservoir computing with a single time-delay autonomous Boolean node

I do not yet have a PYNQ board or any software. I thought I’d use a UbuntuOS machine to host a PYNQ-Z1, and go from there. What are some recommended tools to (1) compile the Verilog code, (2) get it running on the PYNQ FPGA (as an overlay? something else?), (3) feed data into the FPGA circuit and collect the output. Any other steps I’m missing?

I’m a bit confused by this statement made by another user on another post, in response to question on how to make a custom overlay.

  • “Use VHDL/Verilog, or Vivado HLS or some other design entry method to create the network.”

I thought Vivado HLS is somewhat like an IDE, with a built in Verilog compiler, among other tools. Is that incorrect? One does not simply “use VHDL/Verilog” to create a custom overlay. Verilog can be written in any text editor. It is the compiler that matters, correct?

Many Thanks,
Matt

PS: The older post I referred to above is this one: Create overlay for PYNQ LSTM network