Hi. I’m new to FPGAs, so apologies for the simplicity (and ignorance) of this question. While many developers may use the overlays for creating applications, I’m interesting in low-level Verilog programming in order build and test simple circuits like the ones in this paper: Experiments on autonomous Boolean networks. For example, see the very short snippet of Verilog code on page 2.
module my_osc(s_in,s_out);
wire [20:0] delay /*synthesis keep*/;
assign delay[0] = delay[20] | s_in;
assign delay[1] = ~delay[0];
...
assign delay[20] = ~delay[19];
assign s_out = delay[20];
endmodule
I’d also like to implement circuits with simple input/output, like in Figure 2 of this paper: Reservoir computing with a single time-delay autonomous Boolean node
I do not yet have a PYNQ board or any software. I thought I’d use a UbuntuOS machine to host a PYNQ-Z1, and go from there. What are some recommended tools to (1) compile the Verilog code, (2) get it running on the PYNQ FPGA (as an overlay? something else?), (3) feed data into the FPGA circuit and collect the output. Any other steps I’m missing?
I’m a bit confused by this statement made by another user on another post, in response to question on how to make a custom overlay.
- “Use VHDL/Verilog, or Vivado HLS or some other design entry method to create the network.”
I thought Vivado HLS is somewhat like an IDE, with a built in Verilog compiler, among other tools. Is that incorrect? One does not simply “use VHDL/Verilog” to create a custom overlay. Verilog can be written in any text editor. It is the compiler that matters, correct?
Many Thanks,
Matt
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PS: The older post I referred to above is this one: Create overlay for PYNQ LSTM network
You can use Vivado to compile the Verilod and build a bitstream that cna be downloaded to the board.
You can connect the IO of your Verilog design to IO on the board E.g. LEDs, switches, or you can connect them to the Zynq PS (Processing System - ARM processor) and control it from Python.
I made a video of a simple HDL design here:
I see where you are confused. Yes, you can write code in a text editor. The line you quote assumes you will run the code through design tools to synthesize and build the design.
Vivado is the main Xilinx software.
Vivado HLS is a component of this. It allows you to write C code to describe your design instead of Verilog. If you want to do low level Verilog designs, you can ignore HLS for now.
Let me know if anything is unclear.
Cathal
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Thanks very much, Cathal! That helps a lot. It’s still a bit murky to me but hopefully your video along with some additional homework will get me where I want to be.
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HI Matt,
I have been doing a lot of “plain HDL” Verilog development on the Pynq as of late. The first thing I would recommend is that you remove the SD card and set the jumpers to boot off of the QSPI flash when just programming the PL. Otherwise, it takes a lot longer to boot the Pynq environment, and the first time you load a bitstream without the Zynq subsystem, Linux will essentially crash. This may cause filesystem corruption.
You do not need the Zynq subsystem IP – at least I do not need it as the Pynq-Z2 has a 125MHz clock. You just need to enable it in the constraints file and connect it when doing the block design. That seems to cut down on the time required for synthesis and bitstream generation.
Rob
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Thanks, Rob! Can you provide any other tips? I’m fairly clueless and have to speculate on what a lot of the terms mean, including “bitstream.” After you write your HDL Verilog, what did/do you compile it with? (Is it compiled to a “bitstream”?) How do you load the bitstream (software tools, bash command, etc.)? What and where is the “constraints file?” What is the definition of “block design?” Hopefully this conveys my level/lack of knowledge.
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Wow. OK. First thing I recommend is to go through the following videos.
https://www.youtube.com/watch?v=SuXkbcK3w9E
https://www.youtube.com/watch?v=Dupyek4NUoI
https://www.youtube.com/watch?v=VMxU4XWVssM
https://www.youtube.com/watch?v=UBsCNPWudww
This is just to get your feet under you. I think those videos should answer most of your immediate questions.
You might also want to watch this video series to get a background in digital design: https://www.youtube.com/user/LBEbooks/playlists
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Matt,
I should also mention that you do not need a board to get started with Verilog or VHDL. You can install Vivado and start writing, testing and simulating designs in Vivado directly. You only need a board when you want to see your design running on actual hardware.
While it is satisfying to see the design working on physical hardware, a good part of my time is spent in simulation.
You can even get started online: https://www.edaplayground.com/
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Super thanks for all those suggestions, Rob! I’m in Colorado too, by the way (Denver). The project I’m interested in pursuing is very non-traditional from the standpoint of standard digital circuit design, and involves neuroscience and genetic algorithms (maybe even “developmental” genetic algorithms). If by chance you have time and interest in potentially collaborating, send me a message at info@binarycognition.com.
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Hi Matt,
Glad to help.
Unfortunately, I no longer live in Colorado. I have been in Chicago a while now. The email address and moniker stuck. I really do miss the mountains.
One thing to consider is seeing if there are any local hackerspaces with people that share your interest in this sort of thing, or at least provide support and inspiration in digital design.
Rob
Hello - I am an experienced Verilog designer hoping to use my TUL-2 board to do FPGA Development as Rob/Matt were doing. I wanted to know if there was any integrated documentation on this process (or is this my opportunity to develop/contribute such)? I will pursue the links above.
I moved away from the pynq board and tried from something much simpler, without the unimportant (to me) bells and whistles, this Upduino 2.0 board.
http://www.gnarlygrey.com/?i=1
Still, my project has stagnated, as I’ve found it pretty difficult to get up to speed on things without being an industry-trained FPGA engineer.
@cathalmccabe I followed your video up to 8:12, but now my Vivado looks different than yours at that point. See my attached screenshot. Why am I not seeing a “Pacakge” tab, an “I/O Ports” tab, or a “Device Constraints” tab? I’m using Vivado 2023.1, so perhaps that’s part of the issue.
Matt
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