Register access to EMIO GPIO interface

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1

I have what should be a very basic question, but I haven’t been able to find an answer. I’ve got a custom overlay and I’m using the EMIO (built-in) GPIO interface on the Zynq IP to communicate with Verilog modules.

My question is how to find the registers associated with this interface so I can communicate in parallel. All the examples I’ve found write or read to or from one pin at a time, which is very slow.

I know I can do this with an AXI interface, but I’m developing this for a class and I want to keep the FPGA design as simple as possible.

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2

Zynq Technical Reference Manual:
https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/General-Purpose-I/O-GPIO
You can find a similar doc for Zynq MPSOC.

Cathal

3

Thanks, but I’m pretty new at this and I need more basic help.

How to I access these registers from Python on a Pynq?

Thanks.