I did an experiment about the FIR. The problem was I can’t see all registers listed in the .hwh file when I use overlay.fir_wrap_0.register_map.
How can I make all of those registers visible in the register_map?
I attached the .hwh and .bit below
fir_o.hwh (249.2 KB)
fir_o.bit (3.9 MB)
SD card image: v3.0.1
Borad: pyqn-z2 (tul)
Vitis: 2021.2.
Hi @zheng_yue,
Welcome to the PYNQ community.
What FIR IP are you using? Can you share a screenshot of your block design?
Mario
Hi @marioruiz
I write the FIR IP, I attached the code below
fir.h (166 Bytes)
fir.cpp (1.1 KB)
Block design here
The issues is that you have two AXI4-Lite ports for the same IP.
PYNQ only supports one. Hence, I suggest you map all your register to the same AXI4-Lite port.
Mario
@marioruiz
Thanks for your quick reply. I have resolved the problem referring to your instruction.
I remove the bundle=CTRL in HLS to avoid creating an extra s_axi interface, packing port=return and port=len into s_axi_control. In the end, the register_map looked like that
