Request Help: RFDC to DMA transfer doesn't complete

Support
1

Hello,

I am working on ADC readout using the RFDC on a Zynq RFSoC 4x2 with PYNQ (Version 3.0.1). The design consists of the RFDC connected to an AXI4-Stream clock converter (to move into the PL clock domain), followed by an AXI4-Stream subset converter that generates TLAST, and then an AXI DMA configured in simple mode (S2MM).

The issue is that when I call:

dma.recvchannel.transfer(buffer)
dma.recvchannel.wait()

wait() raises an error stating that the DMA channel was not started.

To debug this, I manually checked the DMA status registers at different stages:

Before starting the DMA, both the status register read 0x1, indicating the channel is halted.

After issuing the start command but before initiating a transfer, the registers read 0x0, indicating the DMA has left the halted state.

After starting the transfer (but before calling wait()), both registers read 0x5041.

The value 0x5041 indicates that the channel remains in a halted state while not reporting a transfer completion. This suggests that the DMA is not completing the buffer transfer as expected.

I would appreciate any guidance on what may be incorrect in this design. I have attached the block diagram and IP configurations.

Thanks!

Block Diagram:

image
image2888×767 157 KB

Code for the DMA transfer:

# Reset DMA
dma_re.write(0x30, 4)
dma_im.write(0x30, 4)

while (dma_re.read(0x30) & 0x4):
    pass
while (dma_im.read(0x30) & 0x4):
    pass

# Allocate buffers
buff_re = allocate(shape=(buffer_len_samples,), dtype=np.int16)
buff_im = allocate(shape=(buffer_len_samples,), dtype=np.int16)

print("Before starting DMAs")
print(hex(dma_re.read(0x34)))
print(hex(dma_im.read(0x34)))

dma_re.recvchannel.start()
dma_im.recvchannel.start()

print("After start()")
print(hex(dma_re.read(0x34)))
print(hex(dma_im.read(0x34)))

dma_re.recvchannel.transfer(buff_re)
dma_im.recvchannel.transfer(buff_im)

print("After transfer() before wait()")
print(hex(dma_re.read(0x34)))
print(hex(dma_im.read(0x34)))

dma_re.recvchannel.wait()
dma_im.recvchannel.wait()
2

Hi @Emma_P

Welcome to the PYNQ community.

Based on what you’ve described, my guess is that your tlast is not being triggered when you think it should be. My suggestion would be to put ILAs in your Vivado design and check the expected signals are being sent from the subset converter.

3

Hi @Emma_P,

To add to Josh’s comments.

I wrote an extensive blog about this.

Mario