I am using RFSoC 4*2. I have implemented an example, which is based on the ’ base’ overlay, to generate a signal with DAC. Then the signal is read by the ADC and written in the memory using AXI DMA.
However, I have some problems listed below:
1- when I read the values in the memory for the first time, all of them are zero. When I want to read for the second time, I get the following error: RuntimeError: DMA channel not idle
I am using the following code to read the data:
> data_size = 1000
> dma_recv_im = ol.axi_dma_im.recvchannel
> dma_recv_re = ol.axi_dma_re.recvchannel
> output_buffer_re = allocate(shape=(data_size,), dtype=np.uint64)
> output_buffer_im = allocate(shape=(data_size,), dtype=np.uint64)
>
> #for i in range(10):
> # print('0x' + format(output_buffer_re[i], '02x'))
> print("real:")
> dma_recv_re.transfer(output_buffer_re)
> for i in range(10):
> print('0x' + format(output_buffer_re[i], '02x'))
>
> #for i in range(10):
> # print('0x' + format(output_buffer_re[i], '02x'))
> print("imag:")
> dma_recv_im.transfer(output_buffer_im)
> for i in range(10):
> print('0x' + format(output_buffer_im[i], '02x'))
I have enabled the TLAST signal of AXI4-Stream Clock Convertor.
2- I also tried to read the DAC signal using an oscilloscope, but apparently, it does not generate any signal.
Considering these two problems, I think the RFDC block is not working at all. Because of that the memory is also always empty and getting the error that DMA is not idle.
This is usually a problem with the tlast signal on the DMA. Although you said you have implemented it, I would recommend attaching an ILA to the S_AXIS_S2MM line on the DMA and checking the tlast signal is triggering on the correct clock cycle.
Also, I would consider concatenating your I and Q signals and using a single DMA. This way you can guarantee the complex data you are receiving is from the same clock cycle. You can separate the concatenated signal into two separate I/Q streams again in the PS.
I’m not able to tell that from the diagram you posted but, even with no direct input, you should still be able to read samples from the ADC. My guess is that there is a problem with your tlast signal on the DMAs.
Thanks for your answer. I am new to the RFSoC boards. I searched about how I can use the ILA to debug and check the tlast signal. A tutorial for debugging is provided here, which connects the board via USB cable to a PC and debugs the design in Vivado.
I was wondering if this is the approach that I can debug my design. If yes, I connected the board to a PC (windows 11) but it’s not recognized.
I have connected the board directly to a PC via the USB port on the board. This article is about how to install Cable Drivers for Xilinx Platform Cable USB II. Should I follow the same steps as I have connected the board directly?
There are cable drivers within the Vivado install you can use. I can’t remember the exact filepath on Windows, but on Linux its within Vivado/<version>/data/xicom/cable_drivers. Maybe that will help.
