Hello, I am working on ADC readout using the RFDC on a Zynq RFSoC 4x2 with PYNQ (Version 3.0.1). The design consists of the RFDC connected to an AXI4-Stream clock converter (to move into the PL clock domain), followed by an AXI4-Stream subset converter that generates TLAST, and then an AXI DMA conf…

Hi @Emma_P Welcome to the PYNQ community. Based on what you’ve described, my guess is that your tlast is not being triggered when you think it should be. My suggestion would be to put ILAs in your Vivado design and check the expected signals are being sent from the subset converter.

Hi @Emma_P , To add to Josh’s comments. I wrote an extensive blog about this. [image] Debugging Common DMA Issues [Part 3] Learn Debugging Common DMA Issues If you frequent the PYNQ forum, one of the most common questions/issues we get is why DMA transfer do …

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marioruiz March 3, 2026, 10:36am 3

Hi @Emma_P,

To add to Josh’s comments.

I wrote an extensive blog about this.

Mario

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