RFSoC 4*2 DAC sampling rate problem

Support
1

Device: RFSoC 4x2 Kit
PYNQ Version: v3.0.

I am rebuilding the RFSoC 4x2 MTS project and have changed the DAC sampling rate to 8G and the ADC sampling rate to 4G.
I successfully loaded this bitstream file in JupyterLab and managed to output a custom waveform to the DAC memory.
When I connected the DAC to the oscilloscope (maximum frequency of 70 MHz) using an SMA cable and set the frequency to 10 MHz in the code, the oscilloscope displayed 5 MHz. What could be causing this discrepancy?

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Below is my code, bit, hwh and RF data converter settings
mts.zip (2.9 MB)

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2

Below is my TCL file. Any help would be greatly appreciated.
mts.zip (3.0 MB)

3

Hi, did you resolve this issue? I’m having a similar problem. Thanks.

4

Hi,

RFSoC4x2 MTS project structured around 8 samples per clock cycle. When you increase it without changing the width converter and BRAM structure your would lose samples. The whole design is made with Xilinx open IPs and two Verilog modules. It is an easy fix.

Best