Hello,
I would like to know if anyone has already try to generate and digitize arbitrary waveforms with a RF SoC and espically with the RF-SoC 4x2 ? In other words, I would like to use RF ADC/DAC as standard ADC(digitizer in baseband)/DAC (AWG in baseband) at GSPS.
I’m fully aware that such an objective requires some HDL developements.
Best regards,
Christian Jammes
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Hi @marioruiz I’m trying to use the same project (on the RFSoC 4x2) to generate arbitrary waveforms at higher sample rates. The default design runs at 4GSPS on both ADCs and DACs.
The limits of the RFSoC 4x2 are 5GSPS for the ADCs and 9.85GSPS for the DACs and I want to reach that sample rates.
I managed to run the Jupyter notebooks 5GSPS (ADC) at 8GSPS (DAC) by updating the block design from Vivado and building it again. It works as expected when I inspect the oscilloscope. However, when I try to push beyond that sample rate (i.e. 9 or 9.85, or even 10 GSPS), the oscilloscope clearly shows that the DAC is still producing signals at 8 GSPS.
These are the steps I followed to update the DAC from Vivado (to get first 8GSPS and then more):
- opened the RF Data Converter block
- Basic > RF-DAC > 16 samples per AXI4-Stream Cycle and “No DUC to Fs/2” for all the DAC tiles
- System clocking > I selected the new sample rate
- I updated the data width of the port connected to match the 16 samples (previously 8 in the original design): hier_dac_replay, axis_broadcaster.
Do you have any idea why is it still emitting signals at 8GSPS even though my RFDC is configured for 9, 9.85 or 10 GSPS? Is it possible that I’m misconfiguring something or could it be because of a wrong clock setting in the jupyter notebook (LMK and LMX)?
These are the system clocking settings and DAC configs for 8GSPS
While the following for 9.85 GSPS: