RFSoC 4x2 QSFP malfunction to obtain a 10GbE connection

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1

For my application, the main idea is to use only one lane of QSFP to obtain a 10GbE connection with the RFSoC 4x2 board.

I instantiated a 10GbE core (PHY+MAC+UDP), by mapping only one lane, and then a connection to a PC or a switch by a QSFP to SFP breakout cable is performed.

I am experiencing a problem with that, because I observe ARP packets transmitted from the board, but no data are received. As far as I am concerned, I think the core code is OK, because it has been validated and used in a ZCU208.

By checking in schematics,

image002
image002810×598 165 KB

it seems that MGTYTX and MGTYRX are swapped. More specifically, it appears the following:

  • MGTYTXP0_128 (Y35) and MGTYTXN0_128 (Y36) are connected to QSFP_TX1_P and _N respectively.

  • MGTYRXP0_128 (AA38) and MGTYRXN0_128 (AA39) are connected to QSFP_RX4_P and _N respectively. Instead, I would expect a connection to QSFP_RX1_P and _N.

It could be compatible with what I have observed (TX packet and NO RX). Furthermore, other different lanes have been tried with no change in the final result.

Is there something I’m not understanding and am missing? Any suggestion? Thank you very much in advance.

2 Likes
2

Hi @atmuriel,

Welcome to the PYNQ community.

Can you share how the 10 G IP is configured?

Mario

3

You could try to do something like this

image
image1021×671 136 KB

And use an xdc file to change the pin polarity.

Mario

1 Like
4

Hello… I’m facing the same issue with RFSoC 4x2… TX is working okay, No RX… @marioruiz can you kindly clarify what should the definitions in the xdc files be to change pin polarity ?

Can anybody confirm single channel 10GbE RX/TX working ?

Also it is reporting some clock issues on dmesg.

$ dmesg | grep axienet
[ 6.875784] xilinx_axienet a0020000.ethernet end1: renamed from eth1
[ 10.046296] xilinx_axienet a0020000.ethernet end1: XXV MAC block lock not complete! Cross-check the MAC ref clock configuration
[ 10.057922] xilinx_axienet a0020000.ethernet end1: configuring for inband/10gbase-r link mode
[ 470.852440] xilinx_axienet a0020000.ethernet end1: Link is Up - 10Gbps/Full - flow control off
[ 471.876454] xilinx_axienet a0020000.ethernet end1: Link is Down
[ 507.716426] xilinx_axienet a0020000.ethernet end1: Link is Up - 10Gbps/Full - flow control off
[ 508.740445] xilinx_axienet a0020000.ethernet end1: Link is Down

5

Hi @osschipdesign,

Welcome to the PYNQ community.

Can you please share how the xdc file is looking like for you for these pins?

Mario

6

Hi @marioruiz… Please find the attached design and its constraints… I am able to do TX only and achieve around 3Gbps data throughput over UDP with static ARP routing..

design_10GbE_mark_one.pdf (168.4 KB)

constraints_xdc.txt (2.3 KB)

7

Are you using a breakout cable?
Would it be possible to use a different GT? This should make the resolution easier.