Xilinx 100G Subsystem documents recommends lane swapping is allowable but the both TX and RX but in schematic it is contrary i.e., TX1 is connected to RX4 and TX4 is connected RX1 when in loopback cable which is voila ting the rule. Is this okay?
we are experiencing an important problem with that.
We instanciate a 10GbE core (PHY+MAC+UDP), by mapping only one lane.
We use a QSFP to SFP breakout cable.
We observe ARP packets transmitted from the board, but no data are received.