My block diagram includes RTL IP. That ip also consists of VHDL components and IP. I generate bit and hwh file. However, I got an error as follow:
overlay=Overlay(“/home/xilinx/jupyter_notebooks/Master/design. Bit”)
error:
CacheMetadataError Traceback (most recent call last)
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:252, in BitstreamHandler.get_parser(self, partial)
251 try:
→ 252 parser = self._get_cache()
253 except CacheMetadataError:
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:228, in BitstreamHandler._get_cache(self)
227 else:
→ 228 raise CacheMetadataError(f"No cached metadata present")
CacheMetadataError: No cached metadata present
During handling of the above exception, another exception occurred:
WrongPolarityConnection Traceback (most recent call last)
Input In [1], in <cell line: 6>()
4 #from pynq.overlays.base import BaseOverlay
5 import pynq.lib.dma
----> 6 overlay=Overlay(“/home/xilinx/jupyter_notebooks/Master/design.bit”)
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py:319, in Overlay.init(self, bitfile_name, dtbo, download, ignore_version, device, gen_cache)
315 super().init(bitfile_name, dtbo, partial=False, device=device)
317 self._register_drivers()
→ 319 self.device.set_bitfile_name(self.bitfile_name)
320 self.parser = self.device.parser
322 self.ip_dict = (
323 self.gpio_dict
324 ) = (
325 self.interrupt_controllers
326 ) = self.interrupt_pins = self.hierarchy_dict = dict()
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/device.py:118, in Device.set_bitfile_name(self, bitfile_name)
116 def set_bitfile_name(self, bitfile_name: str) → None:
117 self.bitfile_name = bitfile_name
→ 118 self.parser = self.get_bitfile_metadata(self.bitfile_name)
119 self.mem_dict = self.parser.mem_dict
120 self.ip_dict = self.parser.ip_dict
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:690, in EmbeddedDevice.get_bitfile_metadata(self, bitfile_name, partial)
689 def get_bitfile_metadata(self, bitfile_name:str, partial:bool=False):
→ 690 parser = _get_bitstream_handler(bitfile_name).get_parser(partial=partial)
691 if parser is None:
692 raise RuntimeError(“Unable to find metadata for bitstream”)
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:254, in BitstreamHandler.get_parser(self, partial)
252 parser = self._get_cache()
253 except CacheMetadataError:
→ 254 parser = RuntimeMetadataParser(Metadata(input=self._filepath.with_suffix(“.hwh”)))
255 except:
256 raise RuntimeError(f"Unable to parse metadata")
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/metadata.py:40, in Metadata(input)
38 if os.path.isfile(input):
39 if str(input).endswith(“.hwh”):
—> 40 return HwhFrontend(_hwhfile=input)
41 elif str(input).endswith(“.xsa”):
42 return XsaFrontend(input=input)
File :25, in init(self, name, type, generic_type, _parent, _children, ref, ext, _timestamp, hierarchy_name, ports, parameters, blocks, modules, busses, _hierarchies, _hwhfile, _element_tree, _root, _logical2physical_portmap, _physical2logical_portmap, _logical2physical_extern_pm, _physical2logical_extern_pm)
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:219, in HwhFrontend.post_init(self)
207 “”"
208 Performs the parsing of the hwh into the metadata model
209 * checks to see if the hwhfile is an XML string or a
(…)
216 * Performs a connectivity pass
217 “”"
218 if self._hwhfile != “”:
→ 219 self.parse()
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:241, in HwhFrontend.parse(self)
238 self._create_external_ports()
240 self.resolve_addressing()
→ 241 self.connect_signals()
243 self.refresh()
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:662, in HwhFrontend.connect_signals(self)
657 dst_signal = dst_core.lookup(
658 f"{c_dst}[port]:{c_dst}[signal]"
659 )
661 if isinstance(signal, Signal) and isinstance(dst_signal, Signal):
→ 662 signal.connect(dst_signal)
663 else:
664 raise ExpectedSignalType(
665 f"{signal} and {dst_signal} were both expected to be of type Signal so that they could be connected"
666 )
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/models/signal.py:122, in Signal.connect(self, sig)
118 “”"
119 Connect this signal to sig
120 “”"
121 if not self.connection_exists(sig):
→ 122 self._check_polarity(sig)
123 self._connections[sig.ref] = sig
124 self.con_refs.append(sig.ref)
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/models/signal.py:108, in Signal._check_polarity(self, sig)
106 if not (self.external or sig.external):
107 if sig.driver == self.driver:
→ 108 raise WrongPolarityConnection(
109 f"{sig.ref} cannot be connected to {self.ref} as they have the same polarity (and are not external)"
110 )
111 else:
112 if sig.driver != self.driver:
WrongPolarityConnection: design_1:axi_interconnect_0[block]:M02_AXI[port]:AWPROT[signal] cannot be connected to design_1:Master_proj_top_0[block]:M02_AXI_0[port]:AWPROT[signal] as they have the same polarity (and are not external)
Could you please let me know if PYNQ is compatible with creating a block diagram like my one? How can I solve the error?