ZYNQ Ultrascale+ FIR DMA

Hello all,

After the MNIST on ZYNQ example, it is time to move to a better and more powerful platform ZYNQ Ultrascale (ARM is more powerful).

This FIR example is based on the previous example here.
Although this is preformed on ZYNQ rather than ZYNQ-Ultrascale+, both platforms are so similar.

In this example we are going to compare both software Python signal filter and HW accelerated filter.

  1. Lets start with the overall block-diagram.
    fir_acc.pdf (385.5 KB)

  2. Take a closer look to the filter block

  3. Make sure both the AXI Master and Slave data width is 32 bit.

  4. The FIR filter block constants and setups:


  1. Synthesis and compile the design and copy the required files to the PYNQ folder.
    The Jupyter notebook example is attached here as well
    fir_filter.ipynb (3.5 KB)

The acceleration rate is over x14 compared to software-based filter:

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