SEM IP on zcu104 board with pynq image ICAP OK is not displayed at terminal

Dear all,

I am using sem ip for my ultrascale plus board ZCU104 with pynq 2.6.0 imag running in it.

I have ported the design from application note fo sem ip for zcu102

initially i tried bare-metal application on zcu104 similiar to zcu102 example and this is functioning fine.

Sem UART:

SEM_ULTRA_V3_1

SC 01

FS 04

AF 01

ICAP OK

RDBK OK

INIT OK

SC 02

O>

here is my design attached.

But afterwards, i have loaded the sem ip bitstream using overlay on zcu104 board. I have initialized the bufgce enabled and cap gnt enabled. I cannot see the ICAP OK Message.

SEM UART LOG:

SEM_ULTRA_V3_1

SC 01

FS 04

AF 01

ICAP

KIndly suggest me.

Kind Regards,

HARISH

Hi Harish,

I’ve never used the UART SEM interface, but I have used the AXI one in the past. Could it be something like the UART buffers are not being flushed in the second case, so you are not seeing the full status being printed? Does the UART interface accept commands? Have you tried sending commands to it?

One thing you could try is building an image with the AXI interface to see if it is working correctly. I know that there is a “TMR Soft Error Mitigation Interface” IP where you can choose either an AXI or a UART interface to the SEM core. So you could perhaps use that selecting the AXI interface and using the MMIO class to interact with the registers to control the SEM IP.

Hope that helps a little,
Shane

Not sure this could help just forward the links here:
https://docs.xilinx.com/r/en-US/pg187-ultrascale-sem/Hardware-and-Software-Setup
Hardware and Software Setup

Even this is on PYNQ the base of any design are still FPGA HDL.
So this reference should not be a huge different.

Dear @briansune ,

Thanks for the info.I have checked the same as you mentioned and found the error more than 2%. In order to reduce the error, i have used 125 MHz and V_Enable 68 . Still there no further improvement to the output and its the same.

Kind Regards,
Harish

Dear @stf ,

I have one more design which used AXI uart connected to GP ports of PS. I have tried the same and found only printing the following:
Init Report:

SEM_ULTRA_V3_1
SC 01
FS 04
AF 01

and jupyter kernel is struct here.

Also one more information i need is :
I tried to access the Pcap cntrl register and checked the value and its already cleared. I am confused here because in baremetal application, I accessed and found 1 and then I cleared to 0. But in case Pynq, after overlay has been loaded and access the register and checked its already 0.
kindly suggest me.

code to access reg :
BASE_ADDRESS = 0xFFCA3008

dev_ctrl = allocate(shape=(1,), dtype=‘u4’)
registers.Register(BASE_ADDRESS, buffer=dev_ctrl)
print(“the value of PCAP_PR is :”,dev_ctrl[0])

kindly let me know any suggestions.

Kind Regards,
Harish

Hi Harish,

I’m not entirely sure you are reading the register when using the allocated buffer. For me, when I try and use the Register class to access the PCAP_CTRL register in the CSU directly the kernel hangs.

BASE_ADDRESS = 0x00FFCA3008
reg = Register(BASE_ADDRESS)
print(reg[0])

I created a simple C version to try and see if I could spot anything.

int main() {
        uint32_t* pcap_pr = get_vaddr(0xFFCA3008);
        uint32_t value = *pcap_pr & 0x00000001;
        fprintf(stdout, "pcap_pr=%u\n", value);
        return 0;
}

This basically does the same as above, it grabs a virtual address for the PCAP_CTRL reg with get_vaddr() (just a simple userspace driver using /dev/mmap), and then it tries to dereference the register and read off the value.

When I run this instead of the kernel hanging I get:

image

It looks like we don’t have access. What is probably the issue here is that in baremetal you have the highest privileges over the entire system. But under Linux you don’t.

There are supposed to be some methods to access these registers using /sys/firmware/zynqmp/config_reg. see here
However, when I tried this I did not have much luck either:
image

However, It looks like it is the same permissions issue.

To solve the permissions issue it appears that you need to change some parameters in the PMU firmware. In particular I think the SECURE_ACCESS_VAL flag in xpfw_config.h needs to be changed from 0 to 1. To change this requires a petalinux recipe to batch and to rebuild the .elf for the PMU firmware in the boot files, there is a bit more info in this forum post here. Unfortunately, I’m not very familiar with this flow so I can’t really guide you any further. However, you might have more luck asking on the embedded linux Xilinx forums.

Hope this helps,
Shane

Dear Shane,

Thanks for the inputs , It was really helpful for me. I have more clarity on the issue now. But before I can proceed further to generate the pynq image on my own for ZCU104. I would kindly request you guide me with a standard procedure to generate the same. In online, I have found different procedures but they do not work of Ultrascale plus devices, as these procedures are made for Pynq z2 boards.

It would be really helpful for me, If you can provide me the standard procedure and roofs file for generating 2.6 image.

Thanking you,

Kind Regards,
K Harish

Hi Harish,

No problem at all.

Shawn does a great job of discussing a 2.6 build here that might be helpful for you. We already ship the 104, so instead of BOARDDIR, you’d just need BOARDS=ZCU104. We’d encourage you to switch to 2.7 if possible, but I remember you saying before that you had a dependency on 2.6.

Hope this helps a bit.

All the best,
Shane

Dear Shane,

Thanks for your inputs. I was able to successfully generate an petalinux image and access the register via root mode. Now i have used the same boot images BOOT.BIN, image.ub and boot.scr and replaced in the image pynq 2.6 and i found that the image boots up but i am getting following error message

xilinx@pynq:~$ sudo echo 0xffca3008 > /sys/firmware/zynqmp/config_reg
-bash: /sys/firmware/zynqmp/config_reg: Permission denied

Kindly suggest me with your inputs

Kind regards
K Harish

Dear @stf ,

I have succesfully built a petalinux image and access the PCAP register via only root user. I have made a bsp and exported to pynq boards and created an OS image pynq 2.6.0 and the image is fully functional but i cannot access the PCAP reg. I think here we need the root privileges for accessing the register, which we don’t have. For me it would really helpful if your can provide me the credentials to access the root user of the image or another case would be a suggestion for me to enable same access to pynq as root while building the pynq image.

kindly let me know more inputs.

kind Regards,
Harish

Hi @imharish63,

The credentials are

  • user: xilinx
  • password: xilinx

If you connect via Jupyter you should be in a root environment already.

Mario

Hi @marioruiz ,

Thanks for your reply.
I want to login to root user via ssh. with xilinx credentials i can only login to user xilinx@pynq. But as we can see there is one reply from your college shane , where he was using root@pynq user. I want to test the same.
Let me know where its possible for us.

Kind Regards,
Harish

I am not aware of the root password. You will need to login as xilinx then switch to root with sudo su

Mario

1 Like

Hi Harish,

Apologies for the late response.

To enable root login you need to change the/etc/ssh/sshd_config file and set PermitRootLogin yes.

You may also need to set the root users password up, if you switch to the root user as Mario suggested you can do this:

sudo su
passwd

However, I don’t think this will solve your issue. Running as sudo should be sufficient, so it looks like the required flag might not have been set correctly when recompiling the PMU firmware. You might have more luck asking on the Xilinx forums about this as I’m not sure how familiar people are with the SEM core in this community.

All the best,
Shane

1 Like

Hi @stf,

Thanks for your inputs @stf , @marioruiz
I was able to build the pynq image and successfully access the the registers
root@pynq:~# echo 0xffca3008 > /sys/firmware/zynqmp/config_reg
root@pynq:~# cat /sys/firmware/zynqmp/config_reg
0x1

I have wrote a terminal python programas below and cannot acces the register

root@pynq:~# python3
Python 3.6.5 (default, Apr 1 2018, 05:46:30)
[GCC 7.3.0] on linux
Type “help”, “copyright”, “credits” or “license” for more information.

from pynq import registers
dev_contrl = registers.Register(0xffca3008)
print(dev_contrl)
Bus error (core dumped)

i have also changed the permissions to 777 of the config_reg and its still the same.
as above.

also after i change permissions and reboot the permissions are reverted back to just root.

Kindly suggest me to retain the permissions after reboot and also any way to access it from terminal using python.

kind regards,
Harish

Hi Harish,

Instead of using the registers.Register() for this particular task I would maybe read/write to the /sys/firmware/zynqmp/config_reg file directly from within the Python script. Can you try that and see if it works?

All the best,
Shane

Dear @stf,

Do we have a get_vaddr library function already available with c or written by you?

also let me know after generating pynq image using custom bsp for zcu104 board. I tried to load the bitstream from terminal and later also load pl.dtbo. but i cannot access the pl periherals like gpio or uartlite. but the same i can access from gpios and uart from pynq. Let me know if there is a means to access these peripherals using C/C++ or terminal.

kind regards,
K harish