You can write directly to the DDR3 from the PL using the AXI HP ports.
This is a HLS tutorial on AXI masters, but it may help you understand what you can do.
https://discuss.pynq.io/t/tutorial-axi-master-interfaces-with-hls-ip/4032/4
If you don’t want to use HLS, you could use a VHDL AXI master controller.
You need to allocate a (contiguous) memory buffer in DRAM, and send the address of this buffer to your PL IP.
This is probably what you want to do.
Cathal