Tutorial: AXI Master interfaces with HLS IP

Thanks for your update. It ran successfully.

INFO: [SIM 2] *************** CSIM start ***************
INFO: [SIM 4] CSIM will launch GCC as the compiler.
   Compiling ../../../../../src/example_test.cpp in debug mode
   Generating csim.exe
HLS AXI-Stream no side-channel data example
Success HW and SW results match
INFO: [SIM 1] CSim done with 0 errors.
INFO: [SIM 3] *************** CSIM finish ***************

This is how the block design looks like on MPSoC platform. I tested on ZCU104.

Don’t forget setting the data width of S_AXI_HP0_FPD to 32-bit.

And the final results:

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