Stuck at dma.recvchannel.wait() in DMA → DAC → ADC → DMA Loop

[marioruiz]

Hi @StevenG,

Welcome to the PYNQ community.

I wrote a series of blogs to add ILA in the design to debug this type of issues.
I would suggest you add ILAs at different points in the data path and check if data is flowing.

Designing an Overlay using Vivado Integrated Logic Analyzer (ILA) [Part 1]

Designing an Overlay using Vivado Integrated Logic Analyzer (ILA) In this series of blogs, I will cover how to use the Integrated Logic Analyzer (ILA) to debug your overlay. Instrumenting an ILA should be your last resort when it comes down to debugging. Simulation and co-simulation are the best way to verify your design, although debugging in the actual hardware can be very useful. The main reason for these series of blogs is to address some of the most common issues that are reported in the …

Mario