Support for SGDMA in PYNQ

adimural1002293 · July 4, 2023, 12:52pm

Hello,

Pynq Version is 2.6.0

I’m currently trying to implement FFT algorithm using SGDMA in pynq.

The issue that I’m currently facing is that while calling the transfer method through DMA class , it is always referencing the SDMA class instead of SGDMA class.

Below is the screenshot for that.

even though ol.ip_dict shows that c_include =1.

Tl;dr:
The parameter ‘c_include_sg’ is set to 1 in ol.ip_dict , but still the transfer method of SDMA is being called instead of SGDMA. So my question is whether SGDMA is being supported in Pynq Processor.
If Yes , then what could be the issue here ? Attached below are the files for code, .bit if required.
sgdma_fft-Copy1.bit (3.9 MB)
sgdma_fft-Copy1.ipynb (209.8 KB)

adimural1002293 · July 4, 2023, 12:54pm

In reply to the above , here are some additional screenshots which might help

Edit: As a new user , not able to add more than 1 embedded screenshot

davidnorthcote · July 5, 2023, 10:40am

Hi @adimural1002293

Just a quick message to say that Cyclic Buffer Descriptors are only available in PYNQ v3.0.1.

github.com

Xilinx/PYNQ/blob/93ddd21ab623883590a8c8b07f0b157b2855da4b/pynq/lib/dma.py#L313


      
              if self._cyclic:
                  self._mmio.write(0x0, 0x0004)
                  self._mmio.write(0x0, 0x0000)
              while self.running:
                  pass
              self._transfer_started = False
          
          def _clear_interrupt(self):
              self._mmio.write(self._offset + 4, 0x1000)
          
          def transfer(self, array, start=0, nbytes=0, cyclic=False):
              """Transfer memory with the DMA
          
              Transfer must only be called when the channel is halted
              For `nbytes`, 0 means everything after the starting point.
          
              If the AXI DMA is not configured for data re-alignment then a
              valid address must be aligned or undefined results occur.
          
              For MM2S (send), if Data Realignment Engine (DRE) is not included,
              the source address must be MM2S memory map data width aligned.

Thanks,
David.

adimural1002293 · July 19, 2023, 4:22pm

Hi,

Thank you for the reply.

Just wanted to know if there would be any online resources on SGDMA implementation for Pynq Version 3.0.1 ?