Lvds signal on pynq

Support
1

am working on a project where the plan is that I will interface a AT86RF215 module to the PYNQ eval KIT for testing purposes.The problem I just noticed is, though the says it supports “LVDS”, it has 3.3v on the BANKs where the high speed PMOD goes.

Is it still possible to use it for LVDS input?
I read on the Xilinx forum that it should probably work, but will something strange happen to the input termination?

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2

A “high speed” Pmod port will have traces on the PCB matched, and appropriate pins will be connected to LVDS sets of pins on the FPGA
The Pmods on the Z1/Z2 have not been designed for high speed, and I don’t know if the pin out supports LVDS, or in the configuration you need. Do you have a Pmod with this chip, or do you intend to design your own?

Cathal

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  1. The daughter board I am trying to interface is given in link below
    https://www.microchip.com/developmenttools/ProductDetails/ATREB215-XPRO

  2. LVDS signaling rate is 64 Mhz with 100-ohm impedance and double data rate

4

Which “PYNQ kit” are you using?

The connectors on the daughter board you linked are Sata. How are you planning to physically connect this?
@64MHz, it is very unlikely to work with the Z1 and Z2. We’ve tried the Pmods and got about 10 MHz to 15 MHz before running into signal integrity issues.

Cathal

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I am using zynq z1 kit
I have made a SATA cable for connection between two.
The VCCO of zynq z1 banks is 3.3V. Is that the issue too there? As it is not allowed on ZYNQ devices to interface LVDS differential signals on a bank where VCCO is 3.3V

6

Can I use the HDMI connector as an interface for my LVDS signals coming from daughter board to the ZYNQ. And Impedance matching for HDMI connector is ok with 100 ohm resistance. Am I right?

Saeed

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Yes, 3.3V LVDS would be an issue too. This isn’t supported on Zynq devices.

8

Sorry, I seem to be cross posting with your replies.

Yes, the HDMI port would be a much better option for high speed signals. Yes, each signal has single ended impedance of 50 Ω with 100 Ω for the differential pair.
You can check schematic here if you need to:

Cathal

9

I have seen the schematic and was going through the .xdc file and it says that voltage level setting of HDMI is TMDS_33.

set_property -dict {PACKAGE_PIN W20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_n[0]}]
set_property -dict {PACKAGE_PIN V20 IOSTANDARD TMDS_33} [get_ports {hdmi_in_data_p[0]}]

What if I change this level setting to LVDS_25

Saeed

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10

LVDS_25 should be OK. The main thing you would need to check is if this impacts any other pins on the same back. If you don’t care about any other peripherals, this should be fine.
I’d suggest open a design in Vivado, or try a pin planning project to check this.

Cathal

11

Hi…I am working with the TI ADS5400 EVM and the ADC-FMC-ADAPTER Rev 3 which is used to allow the ADS5400EVM to be used with xilinx FPGA. The signals from the adapter board need to map to LVDS IOs on the FPGA. There is one set of pins on the adapter that connect to pins of the FPGA with IO standard LVCMOS18. I found table 1-55 in ug471 that LVCMOS18 has IO bank availability for both HR and HP, the input/output voltage is 1.8 V and the LVDS has IO bank of HP with input/output voltage of 1.8 V. From looking at this, it seems to me that IOSTANDARD LVCMOS18 will support LVDS signals. I am just looking for some confirmation on this before I hook up the boards and apply power.