I am using Vivado 2019.2, vivado_hls, PYNQ 2.7, and the ZCU111 board. is it fine to use vivado 2019.2 for PYNQ 2.7 or should i upgrade to the new version of Vivado to not face any internal version issues .
I have assigned TLAST in my HLS design. It has a 1 bit data width, but when it comes to ILA debugging, it shows zero.
I checked my IP with ILA. To complete the DMA transaction, the TLAST signal is set to zero; it should be the rising edge of the trigger. How I can set the TLAST for rising edge of the trigger? any suggestions ?
Are you asserting TLAST in your code?
The window in the ILA you are showing does not seems to be completed.
I have assigned the TLAST in the HLS code. But in the ILA it shows zero, so how can I turn to the rising edge of the trigger?
You can watch this video to learn how to use the ILA.
Logic Debug in Vivado controls
Do you mean my ILA debugging process is wrong?
Towards the end the video cover your question: “so how can I turn to the rising edge of the trigger?”
I have changed TLAST from 0 to 1 in the HLS, so the trigger edge is raised but the DMA transaction is not completing.
can you give any suggestions?
These type of questions are outside of the scope of the PYNQ support.
I suggest you familiarize yourself with AXI4-Stream and how the DMA works. As you will learn from the link below,
TLAST signals the last byte of the stream so it cannot be asserted all the time.
A good starting point here How-AXI4-Stream-Works
You can also review Cathal’s tutorial Tutorial: using a HLS stream IP with DMA (Part 1: HLS design), you can add ILA in that design so you can learn how it is working.
Thank you for your suggestions