shiqi17
November 27, 2023, 1:16pm
1
Seeing a lot of articles mentioning the use of DMA to set up the TLAST signal, I use HLS to create the IP cores, connect in vivado. Where and where should the TLAST signal be set in which software?
1 Like
Hi @shiqi17 ,
I would suggest you familiarize yourself with the AXI4 standard and in particular the stream version.
There are a few post in the forum that deals with this, for instance:
Hi everyone.
I am using Vivado 2019.2, vivado_hls, PYNQ 2.7, and the ZCU111 board. is it fine to use vivado 2019.2 for PYNQ 2.7 or should i upgrade to the new version of Vivado to not face any internal version issues .
I have assigned TLAST in my HLS design. It has a 1 bit data width, but when it comes to ILA debugging, it shows zero.
HLS summary
[Screenshot from 2022-06-07 19-15-05]
Vivado IP:
[Screenshot from 2022-06-07 19-34-38]
ILA Waveform
I checked my IP with ILA. To complete the D…
Hello all,
I’m using an axis interface for data in and out (eventually using DMA) but with floating point type. So i need to set the TLAST signal manually, as a million tutorials suggested. But in my case, it doesn’t get synthesized for some reason.
Here is my code:
void fit(hls::stream<axis_t> &in, hls::stream<axis_t> &out, float lambda, float gamma) {
#pragma HLS INTERFACE axis port=in
#pragma HLS INTERFACE axis port=out
#pragma HLS INTERFACE s_axilite port=lambda
#pragma HLS INTERFACE s_a…
Code example here: https://github.com/Xilinx/Vitis-HLS-Introductory-Examples/tree/master/Interface/Streaming
Mario
