I have a project in which I need to combine two AXI-Streams into one (order doesn’t matter). For this, I thought to write small test hardware and a notebook to test it. I am using the AXIS switch in round-robin mode and then the AXIS Subset Converter to generate the TLAST signal. I have included the .tcl file needed to generate the project as well as the bitstream (and .hwh file).
I am running:
PYNQ version 2.7.0 (Git Id: 285d1457e64c076bbb39844afd54b38f075ad2c7)
on PYNQ-Z2 board with Vivado 2020.2
The hardware setup:
The above screenshot is in interface mode to highlight all the connections. The input FIFOs remove the TLAST and TUSER signals. AXIS Switch is in Round-Robin mode to select between the two streams. The AXIS Subset converter generates the TLAST signal (at 128).
The cache is set up for Unsecure Write-Through Transactions.
As a first test, I sent data over just one of the streams (size 128) and tried to receive the stream (size 256) from the DMA. Here itself it is continuously giving DMA Decode Error on the MM2S side and nothing is received on the S2MM side. I then added ILA to figure out what happened.
Here I see multiple problems that I can’t make sense of:
- The input data is always zero despite writing data in the input buffer. (slot 6)
- The TLAST signal is never given in the input. (slot 6)
- The TREADY signal from the DMA (slot 0) goes down before the output buffer (size 256) is filled.
I have attached the .tcl file to recreate the project, the bitstream and hwh files, and the Python Notebook that I am using to test the hardware.
Any help on the topic is greatly appreciated.
try_axis_combine_3_ila.bit (3.9 MB)
try_axis_combine_3_ila.hwh (688.6 KB)
try_axis_combine.tcl (83.3 KB)
stream_combine test.ipynb (9.6 KB)