RF data converter DAC not working

Hi everyone,

I’m trying to implement a RFDC loopback design using DAC to generate a sine wave and measure it using the ADC, and the board is RFSoC 2x2. I have most of the design working, and both the DAC and the ADC were able to generate and collect data. However, what I measured from the ADC seems to be not the data I sent to the DAC.

The inputs to the DAC were generated in Jupyter notebook as follows:

freq_offset = 1234e-3
sampling_rate = 4.096e9
freq = (1000 - freq_offset) * 1e5
max_dac_bit = 14

def DAC_input_format(y_in_arr, dac_bit, dac_buffer_size):
    out_arr = np.clip(y_in_arr*2**(dac_bit-1), -2**(dac_bit-1)+1, 2**(dac_bit-1)-1).astype(np.int16)*2**2
    return np.asarray(np.invert(out_arr)+1, dtype=np.int16)

x_in = 2 * np.pi * np.arange(buffer_size) / sampling_rate

y_in = np.sin(x_in*freq)

y_out = DAC_input_format(y_in, max_dac_bit, buffer_size)

for i in range(buffer_size):
    input_buffer_0[i] = y_out[i]

Here are the first 100 data points in the numpy array that I sent to the DAC, which are from a sine wave with a frequency of ~100 MHz.

Here are the first 100 data points in the data measured by the ADC, which are totally different from what the DAC received.

And here are the settings I used for the ADC:

And here are the settings I used for the DAC:

For clocks and sampling rate, I used 4.0 GSPS for the ADC, and 4.096 GSPS for the DAC. The ADC outputs a clock of 250 MHz, while the DAC outputs a clock of 256 MHz.

Following is the block diagram of my design.
design_1.pdf (218.9 KB)

If anyone could spot any issues with the RFDC settup I would really appreciate your help. Thank you very much in advance!

Best,
Zhimu

1 Like

Hi @ZhimuG

What is your RFDC output clocks? Did you validate your signal with Frequency Planner?

Best

1 Like

Hi @mtsanic

Thank you very much for you reply. I had the RFDC output clocks set to the same as the required AXI4-stream clocks, which are 250 MHz for the ADC and 256 MHz for the DAC. I tried the frequency planner but I don’t really know what I should be looking for there. Sorry I don’t have much experience in designing this DAC-ADC loopback structure.

Best

1 Like