I’ve got an overlay with PS -> DMA MM2S -> FIFO (in packet mode) -> User Cores -> FIFO -> DMA S2MM -> PS. From looking in the System ILA I can see that when I kick off a transfer (in the same manner I’ve been doing from python with other bitstreams) my data gets sent in as I’d expect. The correct number of samples and their content are sent in bursts that make sense based on the DMA core’s config.
After this transfer the MM2S_DMASR (status reg) reports 0x5041: Halted due to a DMADecErr, with an error interupt. Any further attempt to use the core to send gets “RuntimeError: DMA channel not started”. Which makes sense as the core is halted.
Unfortunately the following clears the error but does not allow use of the core:
resulting in “RuntimeError: DMA channel not idle”. Per the Xilinx DMA docs the DMA will report not idle until the first transfer after a reset. Perhaps there is something in pynq.lib.dma.DMA that also needs resetting, for that matter a reset() helper might be helpful here.
As to why I’m getting here in the first place, I’m really not sure.
This config (with unaligned support off) is what I’ve used in a number of overlays routed to a PS HPC Slave with 128 bit width through a smartconnect.