Understanding AdcChannel Class in RFSoC4x2 Xilinx Example

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Hello, I’m currently studying this design on RFSoC4x2 board: RFSoC-PYNQ/boards/RFSoC4x2/base/notebooks/rfdc/01_rf_dataconverter_introduction.ipynb at master · Xilinx/RFSoC-PYNQ · GitHub

I was looking at the file hierarchies.py: RFSoC-PYNQ/boards/RFSoC4x2/packages/rfsystem/package/rfsystem/hierarchies.py at master · Xilinx/RFSoC-PYNQ · GitHub

I’m not able to understand the working of the transfer method of AdcChannel class:

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transfersize = int(np.ceil(packetsize/8))

Why do we divide packetsize by 8?

buffer_re = allocate(shape=(transfersize*8,), dtype=np.int16)
buffer_im = allocate(shape=(transfersize*8,), dtype=np.int16)

If we have set _pgen.packetsize as (packetsize/8), then why do we allot dma buffer memory like this instead of (shape=(transfersize,), dtype=np.int16)?

re_data = np.array(buffer_re) * 2**-15
im_data = np.array(buffer_im) * 2**-15

Lastly, why do we multiply received data by 2**-15?

Thanks.

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So I have been able to understand this piece of code, I’ll drop the explanation here in case someone else is also working on this.

Why do we divide packetsize by 8?
We consider 16 bits of data as one sample, and the bit width of packet generator input is 128 bits, so it receives 8 samples in every clock cycle. To collect n samples of 16 bits each, we need to do n/8 data transfers of 128 bit data.

If we have set _pgen.packetsize as (packetsize/8), then why do we allot dma buffer memory like this instead of (shape=(transfersize,), dtype=np.int16)?
n samples of 16 bit data = n/8 samples of 128 bit data

Lastly, why do we multiply received data by 2**-15?
Each sample of receiver data is a 16 bit fixed point value. Since we are transmitting a sin wave, we need all samples to be in the range [-1, 1]. 2**-15 is a scaling factor that converts 16 bit fixed point data into 64 bit floating point data (double data type) in the range [-1, 1].

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