Understanding AdcChannel Class in RFSoC4x2 Xilinx Example

Hello, I’m currently studying this design on RFSoC4x2 board: RFSoC-PYNQ/boards/RFSoC4x2/base/notebooks/rfdc/01_rf_dataconverter_introduction.ipynb at master · Xilinx/RFSoC-PYNQ · GitHub

I was looking at the file hierarchies.py: RFSoC-PYNQ/boards/RFSoC4x2/packages/rfsystem/package/rfsystem/hierarchies.py at master · Xilinx/RFSoC-PYNQ · GitHub

I’m not able to understand the working of the transfer method of AdcChannel class:

transfersize = int(np.ceil(packetsize/8))

Why do we divide packetsize by 8?

buffer_re = allocate(shape=(transfersize*8,), dtype=np.int16)
buffer_im = allocate(shape=(transfersize*8,), dtype=np.int16)

If we have set _pgen.packetsize as (packetsize/8), then why do we allot dma buffer memory like this instead of (shape=(transfersize,), dtype=np.int16)?

re_data = np.array(buffer_re) * 2**-15
im_data = np.array(buffer_im) * 2**-15

Lastly, why do we multiply received data by 2**-15?