PYNQ: PYTHON PRODUCTIVITY

Use of UART on PYNQ-Z2

I have some questions about using UART on PYNQ-Z2, I’m using Zynq for my first time, so I’m still new to this. Thanks in advance :slight_smile:

From the schematics of the board, the MIO 14 & 15 pins are connected to the FTDI chip.
From UG585-TRM of Zynq “Table 2-4 MIO-at-a-Glance” below, UART 0 can be set to pins 10-11, 14-15, and others.
That means that for this particular board, we should only use pins 14-15 for UART0, right?
What will happen if I set up MIO 10-11 pins for example instead in the MIO Configuration in Vivado?
And how can I use UART1 since it doesn’t use MIO 14-15 pins?

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Something else, Can I solder a two-pin header in the place of J13 and connect them directly with PL pins through Pmod for example? I thought of this instead of using an external USB-UART bridge module, why not use the on-board bridge itself, but should we configure the MIO 14-15 pins to some state in that case to prevent interfacing/multiple drivers?

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Thanks

You are looking at what is possible inside the chip. This is useful if you are designing your own custom board. As you are using the PYNQ-Z2 the physical pins and interfaces are fixed, so you must make connections to the correct pins on the board
MIO 14/15 are connected to physical pins on the board (FTDI chip and USB JTAG port). Internally UART0 needs to be conencted to is connected to these pins, otherwise you won’t be able to access it via the USB JTAG port.

I’m not sure why you want to solder a different header on J13. If you don’t connect anything to MIO14/15 then nothing is connected to the J13 pins.

The UART can be connected back to the PL (instead of MIO pins). You could then route it to PL pins. E.g. Pmod, as you mentioned.

UART0 is used for the linux terminal output. If you connect this to the PL, a bitstream must be loaded with the correct IP for you to access the UART. Loading different bitstreams could cause problems. This is one reason not to do it like this.

Cathal

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Thanks for your reply. Well, I want to have a communication channel between the computer and PL directly, without the use of the PS (no use of Linux or even bare-metal, just use zynq as an FPGA). I will implement my own UART interface controller in the PL in that case.
So since this jumper is connected to the output of the FTDI chip, can I connect it to any PL pin? I drew it below.

Just to confirm, so this means that to use UART1 I can only route it to the PL via EMIO, but not MIO since there are no external physical connections to any of its possible MIO pins, right?

Thanks

A conclusion is that yes you can use J13 as a connection to the USB-UART bridge on board, and connect it with jumpers to PL pins.

Yes